1
Melanie M Chow, John E Cronin, William L Guthrie, Carter W Kaanta, Barbara Luther, William J Patrick, Kathleen A Perry, Charles L Standley: Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias. International Business Machines Corporation, Robert J Haase, John A Stemwedel, December 6, 1988: US04789648 (311 worldwide citation)

Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive mat ...


2
John E Cronin, Carter W Kaanta: Reducing pitch with continuously adjustable line and space dimensions. International Business Machines Corporation, Howard Walter Jr, Whitman Curtis Whitham & McGinn, August 18, 1998: US05795830 (199 worldwide citation)

A method of forming sub-lithographic elements and spaces therebetween where the pitch may be reduced with continuously adjustable line and space dimensions, and a structure resulting from the method, are disclosed. A plurality of spaced convertible members are formed on a substrate. A portion of eac ...


3
George C Correia, John E Cronin, Edmund J Sprogis: Stacked chip process carrier. International Business Machines Corporation, Robert A Walsh Esq, Scully Scott Murphy & Presser, August 28, 2001: US06279815 (148 worldwide citation)

The present invention provides an apparatus and methods for holding a first semiconductor device in proper alignment to a second semiconductor device, whose size is different from the first device, while performing a C4 bond between the two devices. The apparatus for holding the two devices in prope ...


4
John E Cronin, Rosemary A Previti Kelly, James G Ryan, Timothy D Sullivan: Cooling microfan arrangements and process. International Business Machines Corporation, Stephen J Limanek, July 5, 1994: US05326430 (143 worldwide citation)

A micro electrostatic cooling fan arrangement is provided which includes a heat source having a planar surface, a stator attached to the heat source, an axle attached to the heat source and spaced from the stator, a rotary element including a hub having an aperture therein and a fan blade, the axle ...


5
John E Cronin, Pei ing P Lee: Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit. International Business Machines Corporation, Sughrue Mion Zinn Macpeak & Seas, October 9, 1990: US04962058 (135 worldwide citation)

A process of forming a multi-level semiconductor metallization structure from a single deposit layer of metal. The process provides the versatility of allowing stud-up, stud-down, thick and/or thin metallization structure lines to be formed from the single layer of metal. The thick metallization str ...


6
William J Cote, John E Cronin, William R Hill, Cheryl A Hoffman: Endpoint detection apparatus and method for chemical/mechanical polishing. International Business Machines Corporation, William D Sabo, May 3, 1994: US05308438 (127 worldwide citation)

An apparatus and method for determining a selected endpoint in the polishing of layers on a workpiece in a chemical/mechanical polishing apparatus where the workpiece is rotated by a motor against a polishing pad. When a difficult to polish layer, i.e., one requiring a chemical change in a surface s ...


7
Albert S Bergendahl, Claude L Bertin, John E Cronin, Howard L Kalter, Donald M Kenney, Chung H Lam, Hsing San Lee: Method of making shadow RAM cell having a shallow trench EEPROM. International Business Machines Corporation, Heslin & Rothenberg, March 21, 1995: US05399516 (93 worldwide citation)

A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the se ...


8
Kenneth E Beilstein Jr, Claude L Bertin, John E Cronin, Wayne J Howell, James M Leas, Robert B Phillips: Electronic modules with interconnected surface metallization layers and fabrication methods therefore. International Business Machines Corporation, Heslin & Rothenberg, November 14, 1995: US05466634 (77 worldwide citation)

Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer i ...


9
Kenneth E Beilstein Jr, Claude L Bertin, John E Cronin, Wayne J Howell, James M Leas, David J Perlman: Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging. International Business Machines Corporation, Heslin & Rothenberg P C, October 22, 1996: US05567654 (76 worldwide citation)

A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary su ...


10
John E Cronin, Paul A Farrar Sr, Robert M Geffken, William H Guthrie, Carter W Kaanta, Rosemary A Previti Kelly, James G Ryan, Ronald R Uttecht, Andrew J Watts: Plural level chip masking. International Business Machines, Perman & Green, June 30, 1992: US05126006 (73 worldwide citation)

A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are ...



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