1
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, Michael E Whitham, Eugene I Shkurko, Mark F Chadurjian, November 19, 2002: US06483156 (132 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


2
Kerry Bernstein, John A Bracchitta, William J Cote, Tak H Ning, Wilbur D Pricer: Intralevel decoupling capacitor, method of manufacture and testing circuit of the same. International Business Machines Corporation, Anthony J Canale, McGinn & Gibb PLLC, January 13, 2004: US06677637 (37 worldwide citation)

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric ...


3
John A Bracchitta, Wilbur D Pricer: Electrically alterable antifuse using FET. International Business Machines Corporation, John J Goodwin, October 10, 2000: US06130469 (26 worldwide citation)

An integrated circuit and fabrication method for an antifuse structure that includes a shallow trench oxide isolation region disposed in a silicon substrate, the oxide in the trench having a top surface recessed below the surface of the substrate to form sharp corners at each side of the trench. The ...


4
John A Bracchitta, James S Nakos: NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area. International Business Machines Corporation, Mark Chadurjian, Connolly Bove Lodge & Hutz, April 16, 2002: US06373095 (26 worldwide citation)

A field effect floating gate transistor forming an NVRAM cell is disclosed. A substrate having field isolation structures includes therebetween a doped region forming a channel connecting a source and drain. An oxide layer is disposed over said channel forming a tunneling oxide layer for the device. ...


5
John A Bracchitta, Gabriel Hartstein, Stephen A Mongeon, Anthony C Speranza: Method of making a diffused lightly doped drain device with built in etch stop. International Business Machines Corporation, Howard J Walter, Whitham Curtis Whitham & McGinn, May 21, 1996: US05518945 (23 worldwide citation)

A method of fabricating a lightly doped drain MOSFET device with a built in etch stop is disclosed. After forming a gate electrode on a substrate through conventional methods, a conformal doped layer is deposited on the gate electrode. A conformal layer of nitride is then deposited on the conformal ...


6
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, William D Sabo, Whitham Curtis & Christofferson P C, December 9, 2003: US06660596 (23 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


7
Kerry Bernstein, John A Bracchitta, William J Cote, Tak H Ning, Wilbur D Pricer: Intralevel decoupling capacitor, method of manufacture and testing circuit of the same. International Business Machines Corporation, Anthony J Canale, McGinn & Gibb PLLC, April 19, 2005: US06882015 (22 worldwide citation)

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric ...


8
John A Bracchitta, Jack A Mandelman, Stephen A Parke, Matthew R Wordeman: Pillar CMOS structure. International Business Machines Corporation, William N Hogg, August 8, 2000: US06100123 (20 worldwide citation)

A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N.sup.+ and P.sup.+ diffusions in the P and N wells respectively. A unitary pillar of the epita ...


9
Kerry Bernstein, John A Bracchitta, William J Cote, Tak H Ning, Wilbur D Pricer: Method of manufacturing an intralevel decoupling capacitor. International Business Machines Corporation, McGinn IP Law Group PLLC, March 27, 2007: US07195971 (16 worldwide citation)

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric ...


10
James W Adkisson, John A Bracchitta, Jed H Rankin, Anthony K Stamper: Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor. International Business Machines Corporation, Howard J Walter Jr Esq, Ratner & Prestia, July 17, 2001: US06261895 (13 worldwide citation)

A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon ...