1
Scott Dion Rodgers, Rohit Vidwans, Joel Huang, Michael A Fetterman, Kamla Huck: Method and apparatus for generating event handler vectors based on both operating mode and event type. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 30, 1999: US05889982 (77 worldwide citation)

A method and apparatus for handling events, such as those which occur in a processor. An event vector is formed by combining event type information indicating a type of event in the processor and mode information indicating an operating mode of the processor. A microcode event handler vector is gene ...


2
Rohit A Vidwans, Wesley D McCullough, Joel Huang, Joseph F Rohlman: Superscalar processor with a multi-port reorder buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 12, 1996: US05574935 (38 worldwide citation)

A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each read port contains a corresponding read enable line, a read data line, and a read transistor stack. Each write port contains a corresponding w ...


3
Jeffrey M Abramson, Haitham Akkary, Atig A Bajwa, Michael A Fetterman, Andrew F Glew, Glenn J Hinton, Joel Huang, Kris G Konigsfeld, Paul D Madland, Prem Pahlajrai: Method and apparatus for executing and dispatching store operations in a computer system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 2, 1997: US05664137 (23 worldwide citation)

A method and apparatus for performing store operations that includes calculating the address and obtaining the data for the store operation. The address represents the memory location to which the data is to be stored. Once the address is calculated and the data obtained, the store operation is comm ...


4
Rohit A Vidwans, Wesley D McCullough, Joel Huang, Joseph F Rohlman: Multi-port register. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 7, 1998: US05777928 (18 worldwide citation)

A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each read port contains a corresponding read enable line, a read data line, and a read transistor stack. Each write port contains a corresponding w ...


5
Joel Huang, Youngweon Kim: Voltage regulator circuit. Samsung Electronics, Clifford A Poff, January 18, 1994: US05280234 (2 worldwide citation)

A voltage regulator circuit includes a variable resistance formed by diode configuration of NMOS depletion transistors connected in a parallel relation with a supply voltage divider connected at a node by a further variable resistance formed by a serial arrangement of NMOS transistors with ground an ...