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Louis N Hutter, Joe R Trogolo: Method of making vertical PNP transistor in merged bipolar/CMOS technology. Texas Instruments Incorporated, Thomas R FitzGerald, Leo N Heiting, Melvin Sharp, August 8, 1989: US04855244 (45 worldwide citation)

A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer ...


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James R Todd, Joe R Trogolo, Andrew Marshall, Eric G Soenen: Method of making schottky diode with guard ring. Texas Instruments Incorporated, Alan K Stewart, Richard L Donaldson, William E Hiller, May 23, 1995: US05418185 (21 worldwide citation)

A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent t ...


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Dan M Mosher, Cornelia H Blanton, Joe R Trogolo, Larry Latham, David R Cotton, Bob Todd: Method of forming complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate. Texas Instruments Incorporated, B Peter Barndt, Richard L Donaldson, October 26, 1993: US05256582 (20 worldwide citation)

The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for ...


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Michael R Seacrist, Joe R Trogolo, Kenneth M Bell: Process for fabricating isolated vertical bipolar and JFET transistors. Texas Instruments Incorporated, B Peter Barndt, James T Comfort, Melvin Sharp, July 3, 1990: US04939099 (19 worldwide citation)

A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal/nitride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121) and a VPNP buried collector (28). Junction ...


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Kenneth M Bell, Joe R Trogolo: N-Channel JFET device compatible with existing bipolar integrated circuit processing techniques. Texas Instruments Incorporated, Mel Sharp, Richard Donaldson, Gary Honeycutt, March 30, 1982: US04322738 (17 worldwide citation)

A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface ...


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Louis N Hutter, Joe R Trogolo: Vertical PNP transistor in merged bipolar/CMOS technology. Texas Instruments Incorporated, Carlton H Hoel, Richard A Stoltz, Richard L Donaldson, October 3, 1995: US05455447 (12 worldwide citation)

A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer ...


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James R Todd, Joe R Trogolo, Andrew Marshall, Eric G Soenen: Schottky diode with guard ring. Texas Instruments Incorporated, Alan K Stewart, Richard L Donaldson, William E Hiller, July 23, 1996: US05539237 (11 worldwide citation)

A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent t ...


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Dan M Mosher, Larry Latham, Bob Todd, Cornelia H Blanton, Joe R Trogolo, David R Cotton: Complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate. Texas Instruments Incorporated, B Peter Barndt, Richard L Donaldson, January 19, 1993: US05181095 (11 worldwide citation)

An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground reg ...


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Fernando D Carvajal, Joe R Trogolo: Hall effect device with surface potential shielding layer. Texas Instruments Incorporated, Richard A Bachand, N Rhys Merrett, Melvin Sharp, April 21, 1987: US04660065 (10 worldwide citation)

A semiconductor Hall effect device having a stable and more controllable offset voltage is formed, in one embodiment, of an N-type silicon epitaxial layer overlying a P-type silicon substrate, and a P+-type region is formed, for example, by ion implantation, in the surface of the epitaxial layer ove ...