1
Gurtej Sandhu, Richard L Elliott, Trung T Doan, Jody D Larsen: IC mechanical planarization process incorporating two slurry compositions for faster material removal times. Micron Technology, July 30, 1996: US05540810 (108 worldwide citation)

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chem ...


2
Gurtej S Sandhu, Richard L Elliott, Trung T Doan, Jody D Larsen: IC mechanical planarization process incorporating two slurry compositions for faster material removal times. Micron Technology, Walter D Fields, November 30, 1999: US05994224 (88 worldwide citation)

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chem ...


3
Gurtej S Sandhu, Richard L Elliott, Trung T Doan, Jody D Larsen: IC mechanical planarization process incorporating two slurry compositions for faster material removal times. Micron Technology, Walter D Fields, March 21, 2000: US06040245 (88 worldwide citation)

The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a CMP process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chem ...


4
Arthur M Wilson, Jody D larsen: Selective slurries for the formation of conductive structures. Texas Instruments Incorporated, Wade James Brady III, Frederick J Telecky Jr, June 26, 2001: US06251789 (4 worldwide citation)

An embodiment of the instant invention is a method of fabricating a semiconductor device with a patterned dielectric layer having an upper surface and an opening with a bottom and sidewalls formed over a semiconductor substrate, the method comprising the steps of: forming a liner layer (layer



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