1
Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Poelzl: Transistor configuration with a shielding electrode outside an active cell array and a reduced gate-drain capacitance. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Gregory L Mayback, February 10, 2004: US06690062 (68 worldwide citation)

The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD ...


2
Ralf Henninger, Franz Hirler, Joachim Krumrey, Markus Zundel, Walter Rieger, Martin Pölzl: Semiconductor component with an increased breakdown voltage in the edge area. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, October 19, 2004: US06806533 (66 worldwide citation)

A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an edge of the cell array. Each of the transistor cells has a control electrode, which is formed in a trench, and the edge cell has a field plate ...


3
Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Pölzl, Heimo Hofer: Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration. Infineon Technologies, Laurence A Grenberg, Werner H Stemer, Gregory L Mayback, February 28, 2006: US07005351 (62 worldwide citation)

A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in eac ...


4
Franz Hirler, Jenoe Tihanyi, Ralf Henninger, Joachim Krumrey, Martin Poelzl, Walter Rieger: Power transistor. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, August 15, 2006: US07091573 (43 worldwide citation)

The power transistor has a trench cell in a semiconductor body. A lower edge of the gate electrode has a profile which is not horizontal, i.e., not planar with respect to the field electrode.


5
Joachim Krumrey, Franz Hirler, Ralf Henninger, Martin Pölzl, Walter Rieger: Transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, May 10, 2005: US06891223 (33 worldwide citation)

Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inact ...


6
Wolfgang Werner, Franz Hirler, Joachim Krumrey, Walter Rieger: Semiconductor arrangement with a MOS-transistor and a parallel Schottky-diode. Infineon Technologies, Laurence A Greenberg, Werner H Stemer, Ralph E Locher, February 14, 2006: US06998678 (30 worldwide citation)

The present invention relates to a semiconductor arrangement with a MOS transistor which has a gate electrode (40), arranged in a trench running in the vertical direction of a semiconductor body (100), and a Schottky diode which is connected in parallel with a drain-source path (D-S) and is formed b ...


7
Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey, Sonja Krumrey legal representative: Monolithic semiconductor switches and method for manufacturing. Infineon Technologies Austria, Dicke Billig & Czaja PLLC, June 5, 2012: US08193559 (18 worldwide citation)

One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to ...


8
Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger: Semiconductor device. Infineon Technologies Austria, Dicke Billig & Czaja PLLC, September 20, 2011: US08022474 (15 worldwide citation)

A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure ...


9
Joachim Krumrey, Franz Hirler, Walter Rieger: Field electrode trench transistor structure with voltage divider. Infineon Technologies Austria, Dicke Billig & Czaja PLLC, December 16, 2008: US07465987 (9 worldwide citation)

A trench transistor structure having a field electrode arrangement formed in trenches is disclosed. In one embodiment, the field electrode arrangement is conductively connected to subvoltage taps of a voltage divider for the purpose of stabilizing the potentials on a longer time scale than dynamic c ...


10
Oliver Haeberlen, Walter Rieger, Lutz Goergens, Martin Poelzl, Johannes Schoiswohl, Joachim Krumrey: Monolithic semiconductor switches and method for manufacturing. Infineon Technologies Austria, Dicke Billig & Czaja PLLC, May 17, 2011: US07943955 (7 worldwide citation)

One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first s ...