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Christopher Paul Miller, Jim Lewis Rogers, Steven William Tomashot: Cached synchronous DRAM architecture allowing concurrent DRAM operations. International Business Machines Corporation, Robert A Walsh, July 28, 1998: US05787457 (145 worldwide citation)

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture includes a synchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coup ...


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Jim Lewis Rogers, Steven William Tomashott: Cache sdram device. Internatl Business Mach Corp &Lt IBM&Gt, May 22, 1998: JP1998-134572

PROBLEM TO BE SOLVED: To provide a cache SDRAM device having a multi-bank architecture and a programmable cache policy. SOLUTION: The cache SDRAM device has an SDRAM bank 104A, a row register 102A, a selection logic gate circuit 121A, and a mode register. The mode register programs a cache SDRAM to ...