1
Te Long Chiu, Jih Chang Lien: Electrically programmable floating gate semiconductor memory device. Texas Instruments Incorporated, John G Graham, March 15, 1983: US04376947 (66 worldwide citation)

An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the ...


2
G R Mohan Rao, John S Stanczak, Jih Chang Lien, Shyam Bhatia: Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer. Texas Instruments Incorporated, James T Comfort, John G Graham, August 29, 1978: US04110776 (59 worldwide citation)

Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying f ...


3
Jih Chang Lien, Hsingya A Wang: Method of fabricating titanium silicide gate electrodes and interconnections. Advanced Micro Devices, Eugene H Valet, Patrick T King, January 13, 1987: US04635347 (55 worldwide citation)

A method for constructing titanium silicide integrated circuit gate electrodes and interconnections is disclosed. The method finds particularly useful applications in metal-oxide semiconductor integrated circuit fabrication. Following standard active and passive circuit component construction, a thi ...


4
Chi Hui Lin, Jeng Ping Lin, Pei Ing Lee, Jih Chang Lien: Method for fabricating split gate flash memory cell. Nanya Technology Corporation, Quintero Law Office, May 11, 2004: US06734066 (49 worldwide citation)

A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of th ...


5
James Juen Hsu, Steven W Longcor, Jih Chang Lien: Nonvolatile memory cell with vertical gate overlap and zero birds beaks. Advanced Micro Devices, James H Phillips, Michael A Lechter, October 21, 1997: US05680345 (45 worldwide citation)

A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form ...


6
Steven W Longcor, Kuang Yeh Chang, Jih Chang Lien, David M Rogers: Electro-static discharge protection device for CMOS integrated circuit inputs. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, January 22, 1991: US04987465 (44 worldwide citation)

An ESD protection device for CMOS integrated circuit inputs is disclosed. Two clamp components, coupled by a current limiting device, couple the pad to the circuitry of the chip. The device prevents damage to the circuit from an ESD of approximately 8000 or more volts at an input terminal.


7
Jih Chang Lien, Te Long Chiu: Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon. Texas Instruments Incorporated, John G Graham, February 1, 1983: US04370798 (39 worldwide citation)

Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon b ...


8
G R Mohan Rao, John S Stanczak, Jih Chang Lien, Shyam Bhatia: Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer. Texas Instruments Incorporated, John G Graham, June 24, 1980: US04208781 (37 worldwide citation)

Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying f ...


9
Te Long Chiu, Jih Chang Lien: Electrically programmable floating gate semiconductor memory device. Texas Instruments Incorporated, John G Graham, August 21, 1984: US04467453 (37 worldwide citation)

An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the ...


10
G R Mohan Rao, John S Stanczak, Jih chang Lien, Shyam Bhatia: Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer. Texas Instruments Incorporated, Mel Sharp, Rhys Merrett, John Graham, October 11, 1983: US04408385 (33 worldwide citation)

Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying f ...