1
Chit Hwei Ng, Jian Xun Li, Kok Wai Chew, Tjin Tjin Tjoa, Chaw Sing Ho, Shao Fu Sanford Chu: Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, March 23, 2004: US06709918 (29 worldwide citation)

A method for making concurrently metal-insulator-metal (MIM) capacitors and a metal resistors in a Cu damascene back-end-of-line process is achieved. The method forms a Cu capacitor bottom metal plate using a dual-damascene process. A Si


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Mei Sheng Zhou, Sheau Tan Loong, Koon Lay Denise Tan, Jian Xun Li, Wing Hong Chiu, Kok Hiang Stephanie Tang: Process improvements in self-aligned polysilicon MOSFET technology using silicon oxynitride. Chartered Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, July 27, 1999: US05930627 (20 worldwide citation)

Silicon enriched silicon oxynitride is used in applications both as an independent etch stop and as a cap layer and sidewall component over polysilicon gate electrodes in order to prevent insulator thinning and shorts caused by a mis-aligned contact mask. In one embodiment a silicon enriched silicon ...


3
Simon Chooi, Mei Sheng Zhou, Jian Xun Li: Self-aligned contact (SAC) etching using polymer-building chemistry. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, Alek P Szecsy, September 7, 1999: US05948701 (13 worldwide citation)

A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a pair of microelectronic structures. There is then formed sequentially upon the su ...


4
Kai Shao, Yimin Wang, Jian Xun Li, Shao Fu Sanford Chu: Method for forming self-aligned channel implants using a gate poly reverse mask. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, June 25, 2002: US06410394 (11 worldwide citation)

A method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insu ...


5
Jian Xun Li, Qing Hua Zhong, Mei Sheng Zhou: Method to form shallow trench isolation structures. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, October 31, 2000: US06140206 (7 worldwide citation)

A method of forming a shallow trench isolation trenches in a silicon substrate of an integrated circuit device is achieved. A silicon substrate is provided. A buffer layer is deposited overlying the silicon substrate. An etching endpoint layer is deposited overlying the buffer layer. A silicon layer ...


6
Purakh Raj Verma, Shao fu Sanford Chu, Lap Chan, Jian Xun Li, Zhen Jia Zheng: Heterojunction bipolar transistor using reverse emitter window. Chartered Semiconductor Manufacturing, Mikio Ishimaru, April 4, 2006: US07022578 (7 worldwide citation)

A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitter structure, an interlevel dielec ...


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Mei Sheng Zhou, Simon Chooi, Jian Xun Li: Method to improve etching of organic-based, low dielectric constant materials. Chartered Semiconductor Manufacturing, George O Saile, Rosemary L S Pike, February 25, 2003: US06524963 (7 worldwide citation)

A method etching an organic-based, low dielectric constant material in the manufacture of an integrated circuit device has been achieved. Organic materials without silicon and organic materials without fluorine can be etched by using, for example, hydrazine or ammonia gas. Organic materials with sil ...


8
Jian Xun Li, Simon Chooi, Mei Sheng Zhou: Method of fabricating a twin hammer tree shaped capacitor structure for a dram device. Chartered Semiconductor Manufacturing, George O Saile, Stephen B Ackerman, August 11, 1998: US05792692 (6 worldwide citation)

A process for fabricating a large surface area, storage node structure, for a DRAM device, has been developed. The storage node structure is comprised of a lower level polysilicon structure, exhibiting a "twin hammer tree" shape, and connected to an upper polysilicon level, exhibiting a "branch" typ ...


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Purakh Raj Verma, Shao fu Sanford Chu, Lap Chan, Jia Zhen Zheng, Jian Xun Li: Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth. Chartered Semiconductor Manufacturing, Mikio Ishimaru, December 6, 2005: US06972237 (3 worldwide citation)

A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure an ...