1
James F Bertone, Bruno DiPlacido Jr, Thomas F Joyce, Martin Massucci, Lance J McNally, Thomas L Murray Jr, Chester M Nibby Jr, Michelle A Pence, Marc Sanfacon, Jian Kuo Shen, Jeffrey S Somers, G Lewis Steiner: Symmetric multiprocessing system with unified environment and distributed system functions. Zenith Data Systems Corporation, Fitch Even Tabin & Flannery, May 14, 1996: US05517648 (72 worldwide citation)

A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assum ...


2
Thomas F Joyce, Ming T Miu, Jian Kuo Shen, Forrest M Phillips: Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page. Honeywell Bull, Faith F Driscoll, John S Solakian, November 15, 1988: US04785398 (61 worldwide citation)

A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user ...


3
George J Barlow, James W Keeley, Richard A Lemay, Jian Kuo Shen, Robert V Ledoux deceased, Thomas F Joyce, Richard P Kelly, Robert C Miller: Recovery method and apparatus for a pipelined processing unit of a multiprocessor system. Bull HN Information Systems, Faith F Driscoll, John S Solakian, March 9, 1993: US05193181 (61 worldwide citation)

The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and assoc ...


4
James F Bertone, Bruno DiPlacido Jr, Thomas F Joyce, Martin Massucci, Lance J McNally, Thomas L Murray Jr, Chester M Nibby Jr, Michelle A Pence, Marc Sanfacon, Jian Kuo Shen, Jeffrey S Somers, G Lewis Steiner, William S Wu, Norman J Rasmussen, Suresh K Marisetty, Puthiya K Nizar: Adaptively generating timing signals for access to various memory devices based on stored profiles. Packard Bell NEC, Fitch Even Tabin & Flannery, September 15, 1998: US05809340 (50 worldwide citation)

Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a m ...


5
William Panepinto Jr, Ming T Miu, Chester M Nibby Jr, Jian Kuo Shen: Data processing system having centralized memory refresh. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, February 23, 1982: US04317169 (40 worldwide citation)

In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory re ...


6
Theodore R Staplin Jr, John J Bradley, Richard L King, Robert C Miller, Ming T Miu, Jian Kuo Shen: Data processing system having synchronous bus wait/retry cycle. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, January 22, 1985: US04495571 (40 worldwide citation)

A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which en ...


7
Deborah K Staplin, Jian Kuo Shen, Ming Tzer Miu: Resource conflict detection method and apparatus included in a pipelined processing unit. Bull HN Information Systems, Faith F Driscoll, John S Solakian, December 17, 1991: US05073855 (38 worldwide citation)

A pipelined processing unit includes an instruction unit stage containing resource conflict apparatus for detecting and resolving conflicts in the use of register and indicator resources during the different phases of instruction execution. The instruction unit includes a plurality of resource regis ...


8
John J Bradley, Robert C Miller, Ming T Miu, Jian Kuo Shen, Theodore R Staplin Jr: Data processing system having data multiplex control apparatus. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, November 10, 1981: US04300193 (37 worldwide citation)

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the c ...


9
Ming T Miu, John J Bradley, Jian Kuo Shen: Microprogrammed system having hardware interrupt apparatus. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, November 20, 1984: US04484271 (31 worldwide citation)

A hardware interrupt apparatus for assigning the microprogrammed control system to the highest priority hardware interrupt requesting service. In a microprogrammed control system having at least one hardware interrupt, the presence of a hardware interrupt request will cause the interruption of the c ...


10
David E Cushing, Romeo Kharileh, Jian Kuo Shen, Ming Tzer Miu: Dual read/write register file memory. Bull HN Information Systems, Faith F Driscoll, John S Solakian, June 12, 1990: US04933909 (26 worldwide citation)

A dual port read/write register file memory includes means for performing a read/modify write cycle of operation within a single system cycle of operation. The register file memory is constructed from one to more (RAM) addressable multibit storage arrays organized to form a dual read port, single wr ...