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Jerrold L King, David J Corisis: Method of manufacturing a bus bar structure on lead frame of semiconductor device package. Micron Technology, Workman Nydegger & Seeley, December 28, 1999: US06008073 (13 worldwide citation)

A semiconductor device package is formed with a lead frame including a plurality of lead members positioned in an array on a first plane along a vertical or z-axis. A die paddle is attached to the lead frame adjacent to the lead members, and a semiconductor die having a plurality of bond pads is sec ...


32
Jerrold L King, David J Corisis: Bus bar structure on lead frame of semiconductor device package. Micron Technology, Workman Nydegger & Seeley, June 22, 1999: US05914529 (12 worldwide citation)

A semiconductor device package is formed with a lead frame including a plurality of lead members positioned in an array on a first plane along a vertical or z-axis. A die paddle is attached to the lead frame adjacent to the lead members, and a semiconductor die having a plurality of bond pads is sec ...


33
Jerrold L King, Jerry M Brooks: Method of forming a stack of packaged memory die and resulting apparatus. Micron Technology, TraskBritt, September 3, 2002: US06445063 (11 worldwide citation)

A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a PCB board. One or more multi-conductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devices and external ...


34
Jerrold L King, Jerry M Brooks: Method of making a semiconductor chip package. Micron Technology, Ormiston & McKinney PLLC, May 15, 2001: US06232213 (10 worldwide citation)

A semiconductor chip package that includes discrete conductive leads in electrical contact with bond pads on a semiconductor chip. This chip/lead assembly is encapsulated within an encapsulating material and electrode bumps are formed through the encapsulating material to contact the conductive lead ...


35
Jerrold L King, Larry D Kinsman, Jerry M Brooks, David J Corisis: Reduced stress LOC assembly including cantilevered leads. Micron Technology, Trask Britt & Rossa, February 16, 1999: US05872398 (9 worldwide citation)

An LOC die assembly including a die dielectrically adhered to the underside of a lead frame. The adhesive is applied over a minimum cross-sectional area and number of attachment points to maximize flexure of leads extending over the active surface of the die. In this manner, flexure of the leads to ...


36
Jerrold L King, Jerry M Brooks: Method of forming a stack of packaged memory die and resulting apparatus. Micron Technology, TraskBritt, October 15, 2002: US06465275 (9 worldwide citation)

A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multi-conductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor dev ...


37
Jerrold L King, Jerry M Brooks: Apparatus for forming a stack of packaged memory dice. Micron Technology, TraskBritt PC, May 24, 2005: US06897553 (8 worldwide citation)

A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multiconductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devi ...


38
Jerrold L King, Jerry M Brooks: Method of forming a stack of packaged memory die and resulting apparatus. Micron Technology, TraskBritt PC, December 11, 2001: US06329221 (8 worldwide citation)

A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a PCB board. One or more multi-conductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devices and external ...


39
Jerrold L King, Larry D Kinsman, Jerry M Brooks, David J Corisis: Reduced stress LOC assembly. Micron Technology, Trask Britt & Rossa, May 16, 2000: US06063650 (8 worldwide citation)

An LOC die assembly including a die dielectrically adhered to the underside of a lead frame. The adhesive is applied over a minimum cross-sectional area and number of attachment points to maximize flexure of leads extending over the active surface of the die. In this manner, flexure of the leads to ...


40
David J Corisis, Tracy Reynolds, Michael Slaughter, Daniel Cram, Leland R Nevill, Jerrold L King: Integrated circuit package alignment feature. Micron Technology, TraskBritt, December 28, 2004: US06836003 (8 worldwide citation)

An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature inc ...



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