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Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, R Michael Ananian, Dorsey & Whitney, April 6, 2004: US06717576 (151 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphic ...


2
Jerome F Duluk Jr, Sushma S Trivedi, Sam Ng, Lindy Fung, Richard E Hessel, Jack Benkual: Apparatus and method for fragment operations in a 3D-graphics pipeline. Apple Computer, R Michael Ananian, Dorsey & Whitney, September 2, 2003: US06614444 (139 worldwide citation)

Apparatus and methods for rendering 3D graphics images. The apparatus include a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a fragment-operations pipeline, coupled to the port and to the output, the pipeline including a stage for p ...


3
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck: Graphics processor with deferred shading. Apple Computer, R Michael Ananian, Dorsey & Whitney, July 22, 2003: US06597363 (133 worldwide citation)

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage ...


4
Jerome F Duluk Jr: Content-addressable memory system capable of fully parallel magnitude comparisons. Flehr Hohbach Test Albritton & Herbert, February 26, 1991: US04996666 (122 worldwide citation)

A content-addressable memory for storing a plurality of words, each word comprising a plurality of data subfields, and each data subfield comprising a plurality of data bits. Query operations simultaneously compare input data to all subfields in all words and selectably test each subfield for either ...


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Jerome F Duluk Jr, Jack Benkual, Shun Wai Go, Sushma S Trivedi, Richard E Hessel, Joseph P Bratt: Graphics processor with pipeline state storage and retrieval. Apple Computer, Dorsey & Whitney, February 25, 2003: US06525737 (112 worldwide citation)

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon ...


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Jerome F Duluk Jr, Richard E Hessel, Joseph P Grass, Abbas Rashid, Bo Hong, Abraham Mammen: Method and apparatus for generating texture. Apple Computer, Flehr Hohbach Test Albritton & Herbert, September 11, 2001: US06288730 (101 worldwide citation)

A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of det ...


7
Jerome F Duluk Jr: Method and apparatus for simultaneous parallel query graphics rendering Z-coordinate buffer. Silicon Engines, Flehr Hohbach Test Albritton & Herbert, January 21, 1997: US05596686 (87 worldwide citation)

Apparatus and method for a Parallel Query Z-coordinate Buffer are described. The apparatus and method perform a keep/discard decision on screen coordinate geometry before the geometry is converted or rendered into individual display screen pixels by implementing a parallel searching technique within ...


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Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck: Deferred shading graphics pipeline processor. Apple Computer, Flehr Hohbach Test Albritton & Herbert, May 8, 2001: US06229553 (86 worldwide citation)

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising a ...


9
Jerome F Duluk Jr: Method and apparatus for span and subspan sorting rendering system. Raycer Incorporated, Flehr Hohbach Test Albritton & Herbert, November 2, 1999: US05977987 (84 worldwide citation)

A data shifting capability that permits sorting the data in addition to searching for obtaining real-time performance in color, with high quality imagery through a simple search of a spacial database based on a rectangularly shaped search region or range search. A sorting Magnitude Comparison Conten ...


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Jerome F Duluk Jr: Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units. Silicon Engines, Flehr Hohbach Test Albritton & Herbert, September 16, 1997: US05669010 (83 worldwide citation)

A two-stage cascaded processor engine for Digital Signal Processing (DSP) utilizing parallel multi-port memories and a plurality of arithmetic units, including adders and multiplier-accumulators (MACs) is described. The engine supports a Single Instruction Multiple Data (SIMD) architecture. Conventi ...