1
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, Michael E Whitham, Eugene I Shkurko, Mark F Chadurjian, November 19, 2002: US06483156 (132 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


2
Jeffrey P Gambino, Jerome B Lasky, Jed H Rankin: Fin field effect transistor with self-aligned gate. International Business Machines Corporation, William D Sabo, Scully Scott Murphy & Presser, February 10, 2004: US06689650 (111 worldwide citation)

The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates ...


3
John R Abernathey, Jerome B Lasky, Larry A Nesbit, Thomas O Sedgwick, R Stiffler Scott: Method of producing a thin silicon-on-insulator layer. International Business Machines Corporation, Mark F Chadurjian, July 22, 1986: US04601779 (88 worldwide citation)

A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown on the epita ...


4
Bruce A Kauffmann, Chung H Lam, Jerome B Lasky: Semiconductor memory cell and memory array with inversion layer. International Business Machines Corporation, Heslin & Rothenberg, March 1, 1994: US05291439 (76 worldwide citation)

A memory cell, suitable for electrically erasable programmable read only memories (EEPROMs), includes direct write cell capability. The memory cell is fabricated on a substrate and uses an inversion source gate disposed above the substrate to generate a depletion source therein. The depletion source ...


5
John R Abernathey, John E Cronin, Jerome B Lasky: Method of forming metal-strapped polysilicon gate electrode for FET device. International Business Machines Corporation, Mark F Chadurjian, July 5, 1988: US04755478 (63 worldwide citation)

A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes are then fo ...


6
Jerome B Lasky: Method of improving silicon-on-insulator uniformity. International Business Machines Corporation, Sughrue Mion Zinn Macpeak and Seas, April 5, 1988: US04735679 (57 worldwide citation)

A method of improving silicon-on-insulator uniformity using polishing. A polishing stop layer of substantially uniform thickness is provided having a first side which is made coplanar with a first side of a thicker layer of semiconductor material. A polishing process is applied to a second side of t ...


7
Jerome B Lasky, Edward J Nowak, Edmund J Sprogis: Power distribution design method for stacked flip-chip packages. International Business Machines Corporation, William H Steinberg, Schmeiser Olsen & Watts, October 21, 2003: US06635970 (50 worldwide citation)

A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted ...


8
James S Nakos, Paul E Bakeman Jr, Dale P Hallock, Jerome B Lasky, Scott L Pennington: Emissivity independent temperature measurement systems. International Business Machines Corporation, Stephen J Limanek, Mark F Chadurjian, July 13, 1993: US05226732 (44 worldwide citation)

An improved contactless temperature measurement system is provided which includes a workpiece, a chamber containing the workpiece with the walls thereof being substantially transmissive to radiation at wavelengths other than a given wavelength and substantially reflective at the given wavelength to ...


9
John R Abernathey, Wayne I Kinney, Jerome B Lasky, Scott R Stiffler: Method of fabricating silicon-on-insulator transistors with a shared element. International Business Machines Corporation, Sughrue Mion Zinn Macpeak and Seas, March 17, 1987: US04649627 (44 worldwide citation)

A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate region below the ...


10
Stephen F Geissler, Josef W Korejwa, Jerome B Lasky, Pai Hung Pan: Oxidation of silicon nitride in semiconductor devices. International Business Machines Corporation, Heslin & Rothenberg, July 18, 1995: US05434109 (44 worldwide citation)

A silicon nitride layer in a semiconductor device is oxidized by exposure to a mixture of an oxygen reactant and a dilute amount of a fluorine-containing compound at a temperature sufficiently high to substantially cause the oxidation of the silicon nitride. Generally, a temperature greater than abo ...



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