1
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Pact XPP Technologies, Kenyon & Kenyon, September 29, 2009: US07595659 (46 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


2
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logical cell array and bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, June 2, 2015: US09047440 (5 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


3
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Bechen PLLC, June 25, 2013: US08471593 (2 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


4
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Kenyon & Kenyon, November 15, 2011: US08058899 (1 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


5
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Data processor chip with flexible bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, February 9, 2016: US09256575

A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.


6
Volker Grossman, Jens Oertel, Thomas Degueldre: Multimedia USB device server. HARMAN BECKER AUTOMOTIVE SYSTEMS, Artegis Law Group, September 19, 2017: US09767059

The present invention relates to a multimedia server means, comprising a plurality of universal serial bus, USB, connections and a processing means configured to establish a one-by-one data connection between a USB data storage device connected to a first one of the plurality of USB connections and ...


7
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Array processor having a segmented bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, April 18, 2017: US09626325

An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array process ...


8
Martin VORBACH, Frank MAY, Dirk REICHARDT, Frank LIER, Gerd EHLERS, Armin NUCKEL, Volker BAUMGARTE, Prashant RAO, Jens OERTEL: Logic cell array and bus system. Kenyon & Kenyon, June 11, 2009: US20090146691-A1

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


9
Martin VORBACH, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. March 22, 2012: US20120072699-A1

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...