1
Jeffrey P Wright, Hua Zheng: Multiple bank memory with auto refresh to specified bank. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, May 6, 1997: US05627791 (192 worldwide citation)

A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes multiple bank memory arrays. A command decoder/controller responds to command signals to initiate, in a first system clo ...


2
Timothy B Cowles, Jeffrey P Wright: Method for writing to multiple banks of a memory device. Micron Technology, Charles Brantley, September 28, 1999: US05959929 (72 worldwide citation)

In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all bank ...


3
Brett Debenham, Kim Pierce, Douglas J Cutter, Kurt Beigel, Fan Ho, Patrick J Mullarkey, Dien Luong, Hua Zheng, Michael Shore, Jeffrey P Wright, Adrian E Ong, Todd A Merritt: Method and apparatus for storage of test results within an integrated circuit. Micron Technology, Dorsey & Whitney, April 2, 2002: US06365421 (67 worldwide citation)

An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests asso ...


4
Jeffrey P Wright, Hua Zheng: Synchronous dynamic random access memory device. Micron Technology, Dorsey & Whitney, December 16, 2003: US06665222 (54 worldwide citation)

A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a ...


5
Brett Debenham, Kim Pierce, Douglas J Cutter, Kurt Beigel, Fan Ho, Patrick J Mullarkey, Dien Luong, Hua Zheng, Michael Shore, Jeffrey P Wright, Adrian E Ong, Todd A Merritt: Method and apparatus for storage of test results within an integrated circuit. Micron Technology, Dorsey & Whitney, February 27, 2001: US06194738 (53 worldwide citation)

An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests asso ...


6
Kevin J Ryan, Jeffrey P Wright: Memory device with multiple internal banks and staggered command execution. Micron Technology, Seed & Berry, May 11, 1999: US05903509 (41 worldwide citation)

In a memory device such as a page-oriented synchronous dynamic random access memory device (SDRAM), a memory array and associated circuitry are divided into multiple internally defined circuit banks. Commands and addresses applied to the memory device affect all internal banks identically, but on a ...


7
Jeffrey P Wright, Hua Zheng: Synchronous memory allowing early read command in write to read transitions. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, September 30, 1997: US05673233 (41 worldwide citation)

A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle ...


8
Jeffrey P Wright, Hua Zheng, Paul M Fuller: High-speed test system for a memory device. Micron Technology, Seed and Berry, October 12, 1999: US05966388 (38 worldwide citation)

A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Te ...


9
Hua Zheng, Michael Shore, Jeffrey P Wright, Todd A Merritt: Structure and a method for storing information in a semiconductor device. Micron Technology, Seed and Berry, April 20, 1999: US05895962 (36 worldwide citation)

A semiconductor device includes a plurality of conductive layers that are formed on the substrate. Two electrically intercoupled sections of a read-only storage element, such as a fuse element, which together compose the storage element, are each formed in a different one of the conductive layers. T ...


10
Jeffrey P Wright, Hua Zheng: Synchronous dynamic random access memory device. Micron Technology, Dorsey & Whitney, January 9, 2001: US06172935 (34 worldwide citation)

A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a ...