1
Jeffrey C Swanson, Debendra Das Sharma, Jason Jones: Reconfigurable FIFO interface to support multiple channels in bundled agent configurations. Hewlett Packard Development Company, July 15, 2003: US06594714 (23 worldwide citation)

A reconfigurable register array structure allows an agent to transmit data from a single channel or in bundled form from multiple channels. The structure makes economical use of valuable chip space by reducing the size of the overall register array system. A coalescing prestage is used to collect da ...


2
Jeffrey C Swanson, Sharon M Ebner, John A Wickeraad: System and method for multiple cycle capture of chip state. Hewlett Packard Development Company, December 9, 2003: US06662313 (16 worldwide citation)

Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A test device includes a state machine responsive to (i) an arm command for transitioni ...


3
Jeffrey C Swanson, Sharon M Ebner, John A Wickeraad: System and method for multiple cycle capture of chip state. Hewlett Packard Development Company, Fulbright & Jaworski, January 29, 2008: US07325164 (10 worldwide citation)

Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to ...


4
Robert J Safranek, Robert G Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S Jue, Arvind A Kumar, Debendra Das Sharma, Jeffrey C Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T Spink, Fulvio Spagna, Rahul R Shah, Sitaraman V Iyer, William Harry Nale, Abhishek Das, Simon P Johnson, Yuvraj S Dhillon, Yen Cheng Liu, Raj K Ramanujan, Robert A Maddox, Herbert H Hum, Ashish Gupta: High performance interconnect. Intel Corporation, Patent Capital Group, April 18, 2017: US09626321 (5 worldwide citation)

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over ...


5
Jeffrey C Swanson, John A Wickeraad: Apparatus and method for tracking flushes of cache entries in a data processing system. Hewlett Packard Development Company, July 8, 2003: US06591332 (5 worldwide citation)

An apparatus and method using a valid bit in a cache entry address first-in-first-out (FIFO) to indicate when a cache entry can be flushed in a coherent memory domain. One embodiment of the invention involves a method for tracking a cache entry in a cache serving data transfers between a coherent me ...


6
Jeffrey C Swanson, John A Wickeraad: Performance adder for tracking occurrence of events within a circuit. Hewlett Packard Development Company, August 10, 2004: US06775640 (4 worldwide citation)

A performance adder for providing a running total of performance values within an integrated circuit chip. The performance adder is triggered by various performance events as determined through multiplexer logic for detecting occurrence of a particular performance event. The multiplexer logic can al ...


7
Jeff Willey, Robert G Blankenship, Jeffrey C Swanson, Robert J Safranek: High performance interconnect link layer. Intel Corporation, Patent Capital Group, September 13, 2016: US09444492 (2 worldwide citation)

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encode ...


8
Ian P Shaeffer, Jeffrey C Swanson: System and method for single point observability of a dual-mode control interface. Hewlett Packard Development Company, July 1, 2003: US06587965 (2 worldwide citation)

The present invention provides for a method and system for external observation of a dual mode control interface, via a single point of entry/exit from a chip. In operation, data is sent into and retrieved from a chip using a single point on the chip. Multiple test methods can be used with the prope ...


9
Venkatraman Iyer, Darren S Jue, Robert G Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C Swanson: High performance interconnect physical layer. Intel Corporation, Patent Capital Group, May 31, 2016: US09355058 (1 worldwide citation)

A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a ...


10
Jeff Willey, Robert G Blankenship, Jeffrey C Swanson: Control messaging in multislot link layer flit. Intel Corporation, Patent Capital Group, August 22, 2017: US09740654 (1 worldwide citation)

A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit retur ...