1
Kenneth T Chin, Jerome J Johnson, Phillip M Jones, Robert A Lester, Gary J Piccirillo, Jeffrey C Stevens, Michael J Collins, C Kevin Coffee: Computer system with adaptive memory arbitration scheme. Compaq Computer Corporation, Michael F Heim, Jonathan M Harris, Conley Rose & Tayon P C, September 4, 2001: US06286083 (154 worldwide citation)

A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, ...


2
Jeffrey C Stevens, Jens K Ramsey, Randy M Bonella, Philip C Kelly: Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, June 28, 1994: US05325503 (62 worldwide citation)

A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop co ...


3
Mike T Jackson, Jeffrey C Stevens, Roger E Tipley: Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, August 2, 1994: US05335335 (54 worldwide citation)

A method and apparatus for enabling a dual ported cache system in a multiprocessor system to guarantee snoop access to all host bus cycles which require snooping. The cache controller includes a set of latches coupled to the host bus which it uses to latch the state of the host bus during a snoop cy ...


4
Jeffrey C Stevens, Mike T Jackson, Roger E Tipley, Jens K Ramsey, Sompong Olarig, Philip C Kelly: Multiprocessor cache abitration. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, June 20, 1995: US05426765 (53 worldwide citation)

A method for arbitrating between processor and host bus snoop accesses to a cache subsystem in a multiprocessor system where the processor does not allow for processor cycle aborts. When a processor access and a snoop access both occur and no tag access or tag modify cycle is currently being perform ...


5
Shaun Wandler, Jeffrey C Stevens, Jeff W Wolford, Robert Woods, Danny Higby, Russ Wunderlich, Todd Deschepper, Jeffrey T Wilson: Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices. Compaq Computer Corporation, Michael F Heim, Jonathan M Harris, Conley Rose Tayon P C, May 1, 2001: US06226700 (39 worldwide citation)

A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes inter ...


6
Charles J Stancil, Jeffrey C Stevens: Computer fan speed system to reduce audible perceptibility of fan speed changes. Hewlett Packard Development Company, July 29, 2003: US06601168 (36 worldwide citation)

A fan speed controller for a computer system that calculates an internal central processing unit temperature and, in response to target fan speeds communicated over a system management bus, slowly adjusts the computer system fan speed such that audible noise associated with the fan speed change is n ...


7
Jeffrey C Stevens, Jens K Ramsey, Randy M Bonella, Philip C Kelly: Cache snoop latency prevention apparatus. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, August 29, 1995: US05446863 (34 worldwide citation)

A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop co ...


8
Jens K Ramsey, Jeffrey C Stevens, Michael E Tubbs, Charles J Stancil: Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, September 22, 1998: US05813022 (31 worldwide citation)

A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowl ...


9
Michael J Collins, Jeffrey C Stevens, Guy E McSwain: Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, August 11, 1998: US05793693 (31 worldwide citation)

A cache memory system utilizing asynchronous/synchronous burst counter circuitry which lessens the need for expensive, high speed data SRAM to achieve zero wait-state operation. The burst counter circuitry takes advantage of the fact that a read address is present on the address bus approximately on ...


10
Jeffrey C Stevens, John E Larson, Gary W Thome, Michael J Collins, Michael Moriarty: Programmable memory controller having two level look-up for memory timing parameter. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, July 7, 1998: US05778413 (25 worldwide citation)

A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (C ...