1
David L Roper, James W Cady, James Wilder, James Douglas Wehrly Jr, Jeff Buchle, Julian Dowden: Pitch change and chip scale stacking system. Staktek Group, Andrews Kurth L, J Scott Denko, May 30, 2006: US07053478 (108 worldwide citation)

The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two int ...


2
James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Julian Dowden, Jeff Buchle: Chip scale stacking system and method. Staktek Group, June 10, 2003: US06576992 (105 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, a pair of CSPs is stacked, with one CSP above the other. The two CS ...


3
Russell Rapport, Jeff Buchle: Clock driver with instantaneously selectable phase and method for use in data communication systems. Staktek Group, J Scott Denko, George &plus Donaldson, August 28, 2001: US06282210 (88 worldwide citation)

A clock driver providing a clock signal, from an input clock signal, that has instantaneously selectable phase and methods for synchronizing data transfers in a multi-signal bus communication system. A clock driver of the present invention generates an output clock signal from an input clock signal ...


4
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, Andrews Kurth, July 5, 2005: US06914324 (73 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


5
James W Cady, Julian Partridge, James Douglas Wehrly Jr, James Wilder, David L Roper, Jeff Buchle: Low profile chip scale stacking system and method. Staktek Group, Andrews Kurth, J Scott Denko, April 11, 2006: US07026708 (64 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided fo ...


6
James W Cady, Julian Partridge, James Douglas Wehrly Jr, James Wilder, David L Roper, Jeff Buchle: Low profile chip scale stacking system and method. Staktek Group, Andrew Kurth, J Scott Denko, August 22, 2006: US07094632 (39 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by ...


7
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, Andrews Kurth, J Scott Denko, October 18, 2005: US06955945 (7 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


8
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Jeff Buchle, Julian Dowden: Stacking system and method. Entorian Technologies, Fish & Richardson P C, February 24, 2009: US07495334 (3 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the ...


9
David L Roper, Curtis Hart, James Wilder, Phill Bradley, James G Cady, Jeff Buchle, James Douglas Wehrly Jr: Modularized die stacking system and method. Entorian Technologies, Fish & Richardson P C, February 3, 2009: US07485951 (2 worldwide citation)

An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. The present invention may be employed to stack similar or dissimilar i ...


10
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, Fish & Richardson P C, August 14, 2007: US07256484 (2 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...