1
Xavier Baie
Brent A Anderson, Xavier Baie, Randy W Mann, Edward J Nowak, Jed H Rankin: High mobility transistors in SOI and method for forming. International Business Machines Corporation, Mark F Chadurjian, Schmeiser Olsen & Watts, September 23, 2003: US06624478 (25 worldwide citation)

The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been ...


2
Xavier Baie
Brent A Anderson, Xavier Baie, Randy W Mann, Edward J Nowak, Jed H Rankin: High mobility transistors in SOI and method for forming. International Business Machines Corporation, Schmeiser Olson & Watts, William D Sabo, November 8, 2005: US06962838 (4 worldwide citation)

The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been ...


3
Xavier Baie
Brent A Anderson, Xavier Baie, Randy W Mann, Edward J Nowak, Jed H Rankin: High mobility transistors in SOI and method for forming. Schmeiser Olsen Watts, December 18, 2003: US20030232467-A1

The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been ...


4
Xavier Baie
Brent A Anderson, Xavier Baie, Randy W Mann, Edward J Nowak, Jed H Rankin: High mobility transistors in soi and method for forming. International Business Machines Corporation, Jack P Friedman, Schmeiser Olsen & Watts, July 31, 2003: US20030141548-A1

The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been ...


5
Douglas S Armbrust, Dale W Martin, Jed H Rankin, Sylvia Tousley: Method to define and tailor process limited lithographic features using a modified hard mask process. International Business Machines Corporation, William D Sabo, Larry J Hume, Connolly Bove Lodge & Hutz, August 26, 2003: US06610607 (187 worldwide citation)

A method to define and tailor process limited lithographic features is provided. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls of the mask. The pattern of the mask and spa ...


6
John M Cohn, Jason Hibbeler, Anthony K Stamper, Jed H Rankin: Circuit layout methodology using a shape processing application. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Richard M Kotulak Esq, March 6, 2007: US07188322 (159 worldwide citation)

A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-s ...


7
David M Fried, Timothy J Hoague, Edward J Nowak, Jed H Rankin: Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same. International Business Machines Corporation, Mark F Chadurjian Esq, Scully Scott Murphy & Presser, June 24, 2003: US06583469 (140 worldwide citation)

A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a source region and a drain region. The channel region has a first horizontal width and the source and dr ...


8
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, Michael E Whitham, Eugene I Shkurko, Mark F Chadurjian, November 19, 2002: US06483156 (132 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


9
Jeffrey P Gambino, Jerome B Lasky, Jed H Rankin: Fin field effect transistor with self-aligned gate. International Business Machines Corporation, William D Sabo, Scully Scott Murphy & Presser, February 10, 2004: US06689650 (111 worldwide citation)

The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates ...


10
James W Adkisson, Paul D Agnello, Arne W Ballantine, Rama Divakaruni, Erin C Jones, Jed H Rankin: Double gate trench transistor. International Business Machines Corporation, Mark F Chadurjian, Whitham Curtis & Christofferson P C, October 29, 2002: US06472258 (95 worldwide citation)

A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is ...