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Jean Pierre Giacalone, Francois Theodorou, Alain Boyadjian: Multiplier accumulator circuits. Texas Instruments Incorporated, Gerald E Laws, W James Brady III, Frederick J Telecky Jr, May 27, 2003: US06571268 (75 worldwide citation)

A multiply-accumulate (MAC) unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a plurality of partial products from said first and second operands, a Wallace tree adder for reducing the partial products and for selectively arit ...


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Jean Pierre Giacalone, Anne Lombardot, Francois Theodorou: Rounding mechanisms in processors. Texas Instruments Incorporated, Gerald E Laws, W James Brady III, Frederick J Telecky Jr, May 16, 2006: US07047272 (42 worldwide citation)

An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate carry results and provides a final output to a final adder 470 connected to the partial production reductio ...


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Gilbert Laurenti, Jean Pierre Giacalone, Emmanuel Ego, Marc Couvrat: Bit field processor. Texas Instruments Incorporated, Robert D Marshall Jr, W James Brady III, Frederick J Telecky Jr, July 6, 2004: US06760837 (23 worldwide citation)

An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is t ...


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Jean Pierre Giacalone, Herve Daniel: Hardware extensions for image and video processing. Texas Instruments Incorporated, Ronald O Neerings, Wade James Brady III, Frederick J Telecky Jr, August 16, 2005: US06930689 (18 worldwide citation)

A processing device (200) includes three hardware extensions: a motion estimation extension 202, a pixel interpolation extension 204 and a DCT/iDCT extension 206. The hardware extensions perform functions which would otherwise be highly processor intensive, resulting in high power consumption and/or ...


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Jean Pierre Giacalone: Hardware extension for accelerating fractional integer division within 3D graphics and MP3 applications. Texas Instruments Incorporated, Ronald O Neerings, Wade James Brady III, Frederick J Telecky Jr, April 6, 2010: US07693929 (3 worldwide citation)

An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of the invention a division operation is performed in no more than two cycles. In another embodiment of the invention, the division operation ...


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Ozgur Oyman, Jean Pierre Giacalone, Ivan Fox: Interactive video conferencing. INTEL CORPORATION, Thorpe North & Western, December 4, 2018: US10148868

A multimedia telephony services over internet protocol (IP) multimedia subsystems (IMS) (MTSI) receiver operable to support region of interest (ROI) signaling with a MTSI sender is disclosed. The MTSI receiver can define a requested region of interest (ROI). The MTSI receiver can map the requested R ...


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Ozgur Oyman, Jean Pierre Giacalone, Ivan Fox: Interactive video conferencing. Intel Corporation, Thorpe North & Western, November 28, 2017: US09832369

Technology for a local user equipment (UE) operable to perform video conferencing with a remote UE is disclosed. The local UE can define a region of interest (ROI) within a field of view of a camera of the remote UE. The local UE can map the ROI to one or more pan, tilt, zoom and focus (PTZF) comman ...


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Ozgur Oyman, Jean Pierre Giacalone, Ivan Fox: Interactive video conferencing. INTEL CORPORATION, Thorpe North & Western, December 6, 2016: US09516220

Technology for a local user equipment (UE) operable to perform video conferencing with a remote UE is disclosed. The local UE can define a region of interest (ROI) within a field of view of a camera of the remote UE. The local UE can map the ROI to one or more pan, tilt, zoom and focus (PTZF) comman ...


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Vladimir Kovacevic, Zdravko Pantic, Aleksandar Beric, Ramanathan Sethuraman, Jean Pierre Giacalone, Anton Igorevich Veselov, Marat Ravilevich Gilmutdinov: Block-based static region detection for video processing. Intel Corporation, Hanley Flight & Zimmerman, August 2, 2016: US09407926

Methods, apparatus, systems and articles of manufacture to perform block-based static region detection for video processing are disclosed. Disclosed example video processing methods include segmenting pixels in a first frame of a video sequence into a first plurality of pixel blocks. Such example me ...