1
Roger D Chamberlain, E F Berkley Shands, Benjamin C Brodie, Michael Henrichs, Jason R White: Firmware socket module for FPGA-based pipeline processing. Exegy Incorporated, Washington University, Thompson Coburn, May 31, 2011: US07954114 (48 worldwide citation)

A firmware socket module is deployed on a reconfigurable logic device, wherein the firmware socket module is configured to provide both commands and target data to an entry point in a data processing pipeline, wherein each command defines a data processing operation that is to be performed by the da ...


2
Roger D Chamberlain, Benjamin M Brink, Jason R White, Mark A Franklin, Ron K Cytron: Intelligent data storage and processing using FPGA devices. IP Reservoir, Thompson Coburn, December 31, 2013: US08620881 (25 worldwide citation)

Methods and apparatuses for processing data are disclosed, including methods and apparatuses that leverage a reconfigurable logic device to offload decompression and search operations from a processor to thereby enable high speed data searches within data that has been stored in a compressed format.


3
Ronald S Indeck, David Mark Indeck, Naveen Singla, Jason R White: Method and system for accelerated stream processing. Exegy Incorporated, Thompson Coburn, February 12, 2013: US08374986 (25 worldwide citation)

Disclosed herein is a method and system for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plural ...


4
David E Taylor, Ronald S Indeck, Jason R White, Roger D Chamberlain: Method and system for high throughput blockwise independent encryption/decryption. IP Reservoir, Thompson Coburn, Benjamin L Volk Jr, May 27, 2014: US08737606 (17 worldwide citation)

An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A cor ...


5
David E Taylor, Ronald S Indeck, Jason R White, Roger D Chamberlain: Method and system for high throughput blockwise independent encryption/decryption. IP Reservoir, Thompson Coburn, Benjamin L Volk Jr, March 17, 2015: US08983063 (16 worldwide citation)

An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A cor ...


6
David E Taylor, Ronald S Indeck, Jason R White, Roger D Chamberlain: Method and system for high throughput blockwise independent encryption/decryption. Exegy Incorporated, Thompson Coburn, February 19, 2013: US08379841 (13 worldwide citation)

An encryption technique is disclosed for encrypting a data segment comprising a plurality of data blocks, wherein the security and throughput of the encryption is enhanced by using blockwise independent bit vectors for reversible combination with the data blocks prior to key encryption. Preferably, ...


7
Michael John Henrichs, Joseph M Lancaster, Roger Dean Chamberlain, Jason R White, Kevin Brian Sprague, Terry Tidwell: Method and apparatus for accelerated format translation of data in a delimited data format. IP Reservoir, Thompson Coburn, April 25, 2017: US09633093 (1 worldwide citation)

Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a fixed field format using pipelined operations. A r ...


8
Ronald S Indeck, David Mark Indeck, Naveen Singla, Jason R White: Method and apparatus for accelerated data quality checking. IP Reservoir, Thompson Coburn, January 17, 2017: US09547824 (1 worldwide citation)

Disclosed herein is a method and apparatus for hardware-accelerating various data quality checking operations. Incoming data streams can be processed with respect to a plurality of data quality check operations using offload engines (e.g., reconfigurable logic such as field programmable gate arrays ...


9
Michael John Henrichs, Joseph M Lancaster, Roger Dean Chamberlain, Jason R White, Kevin Brian Sprague, Terry Tidwell: Method and apparatus for accelerated format translation of data in a delimited data format. IP RESERVOIR, Thompson Coburn, December 4, 2018: US10146845

Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a mapped variable field format using pipelined opera ...


10
Roger D Chamberlain, E F Berkley Shands, Benjamin C Brodie, Michael Henrichs, Jason R White: Firmware socket module for FPGA-based pipeline processing. Exegy Incorporated & Washington University, Thompson Coburn, July 26, 2007: US20070174841-A1

A firmware socket module is deployed on a reconfigurable logic device, wherein the firmware socket module has a communication path between itself and an entry point into a data processing pipeline, wherein the firmware socket module is configured to provide both commands and target data to the entry ...