David J Harriman, Brian K Langendorf, Jasmin Ajanovic: Method and apparatus for arbitrating between command streams. Intel Corporation, Jeffrey S Draeger, July 18, 2000: US06092158 (198 worldwide citation)

A method and apparatus for arbitrating between command streams. The method unblocks high priority commands which are blocked and then selects any remaining high priority commands. Normal priority commands are selected after the high priority commands. A memory controller described includes a command ...

Jasmin Ajanovic, Serafin Garcia, David J Harriman: Method and apparatus for initializing a computer interface. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 16, 2002: US06374317 (112 worldwide citation)

According to one embodiment, a computer system includes a first hub agent and a hub interface coupled to the first hub agent. The first hub agent is adaptable to sample the hub interface in order to detect the presence of a second hub agent upon initiation of the computer system. In a further embodi ...

Jasmin Ajanovic: Controller configurable for use with multiple memory organizations. Intel Corporation, Trop Pruner & Hu P C, October 2, 2001: US06298426 (111 worldwide citation)

A memory controller for use with a memory sub-system selected to have one of multiple memory organizations. The memory controller includes output drivers connected to output pins, the output drivers being programmable to have one of multiple output characteristics. The memory controller also include ...



Nilesh Shah, Jasmin Ajanovic, Dahmane Dahmani: Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 2, 1997: US05664117 (53 worldwide citation)

A bridge circuit providing for efficient data transfer between a first bus and a second bus in a computer system. The bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to the second bus. Fetch circuitry fetches the r ...

Eric R Wehage, Jasmin Ajanovic, David Harriman, David M Lee, Blaise Fanning, Buck Gremel, Ken Creta, Wayne Moore: General input/output architecture, protocol and related methods to manage data integrity. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 19, 2006: US07152128 (52 worldwide citation)

An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link, validating content of one ...


George R Hayek, Radhakrishnan Venkataraman, Jasmin Ajanovic: Time-distributed ECC scrubbing to correct memory errors. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 2, 1999: US05978952 (49 worldwide citation)

Error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Rather, the address of the section or row of RAM that con ...

Michael J Muchnick, Jerry A Verseput, Jasmin Ajanovic: Computer card insertion detection circuit. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 3, 1997: US05636347 (43 worldwide citation)

A personal computer (PC) card insertion method and apparatus uses a subset of connector ground terminals and pins, located at either end of the connector, for detecting the onset of a card insertion. The host PC card slot connector has pull-up resistors for keeping the subset of ground terminals at ...