1
James Y Cho, James B Keller, Mark D Hayter: Memory controller with programmable configuration. Broadcom Corporation, Garlick Harrison & Markison, April 5, 2005: US06877076 (193 worldwide citation)

A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory ...


2
Howard G Sachs, James Y Cho: Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency. Intergraph Corporation, Townsend and Townsend, February 25, 1992: US05091846 (128 worldwide citation)

A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation ...


3
James Y Cho, James B Keller, Mark D Hayter: Memory controller with programmable configuration. Broadcom Corporation, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, September 23, 2003: US06625685 (120 worldwide citation)

A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory ...


4
Mark D Hayter, Joseph B Rowlands, James Y Cho: System on a chip for networking. Broadcom Corporation, Lawrence J Merkel, July 20, 2004: US06766389 (113 worldwide citation)

A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coup ...


5
James Y Cho, Kwong Tak A Chui, Chun H Ning: Page open hint in transactions. Broadcom Corporation, Lawrence J Merkel, February 25, 2003: US06526483 (99 worldwide citation)

A system including an agent and a memory controller, in which the agent may initiate transactions targeting a memory to which the memory controller is coupled and the transactions may include a page hint indication. The page hint indication is transmitted during the transaction by the agent, and may ...


6
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Apparatus for maintaining consistency of a cache memory with a primary memory. Intergraph Corporation, Townsend and Townsend, June 12, 1990: US04933835 (95 worldwide citation)

A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memor ...


7
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Quadword boundary cache system. Intergraph Corporation, Townsend and Townsend, August 22, 1989: US04860192 (82 worldwide citation)

In a cache memory system, multiple-word boundary registers, multiple-word line registers, and a multiple-word boundary detector system provide accelerated access of data contained within the cache memory within the multiple-word boundaries, and provides for effective prefetch of sequentially ascendi ...


8
Howard G Sachs, James Y Cho: Memory address translation system having modifiable and non-modifiable translation mechanisms. Intergraph Corporation, Townsend and Townsend Khourie and Crew, October 19, 1993: US05255384 (75 worldwide citation)

A Cache-Memory Management System provides high speed virtual to real address translation. Address translation logic, comprised of mutually exclusive modifiable and nonmodifiable translation logic, selectively provides real address output responsive to the externally supplied virtual address from the ...


9
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Cache-MMU system. Intergraph Corporation, Townsend and Townsend, February 6, 1990: US04899275 (57 worldwide citation)

A cache and memory management system architecture and associated protocol is disclosed. The cache and memory management system is comprised of a set associative memory cache subsystem, a set associative translation logic memory subsystem, hardwired page translation, selectable access mode logic, and ...


10
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Method and apparatus for addressing a cache memory. Intergraph Corporation, Townsend & Townsend, November 28, 1989: US04884197 (57 worldwide citation)

A microprocessor architecture is disclosed having separate very high speed instruction and data interface circuitry for coupling via respective separate very high speed instruction and data interface buses to respective external instruction cache and data cache circuitry. The microprocessor is compr ...