1
James William Feeney, Howard Thomas Olnowich, George William Wilhelm Jr: Multi-tasking adapter for parallel network applications. International Business Machines Corporation, Shelley M Beckstrand, June 6, 2000: US06072781 (127 worldwide citation)

A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs mes ...


2
Howard Thomas Olnowich, Michael Wayland Dotson, James William Feeney, Michael Hans Fisher, John David Jabusch, Robert Francis Lusch, Michael Anthony Maniguet: Apparatus for coupling a bus-based architecture to a switch network. International Business Machines Corporation, Shelley M Beckstrand, July 17, 2001: US06263374 (66 worldwide citation)

An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interco ...


3
James William Feeney, George William Wilhelm Jr: System having device driver operates in first mode for allowing concurrent access to adapter by applications and second mode for limiting access to one application. International Business Machines Corporation, George E Jenkens & Gilchrist Clark, Richard M Goldman, September 23, 1997: US05671442 (45 worldwide citation)

A data processing system gives an application running on the operating system exclusive ownership of a hardware device. The system is operable in two modes. In the first mode the application interacts with the hardware device by making use of the processing system. In this mode many layers of the pr ...


4
James William Feeney, Howard Thomas Olnowich, George William Wilhelm Jr: Multi-tasking adapter for parallel network applications. International Business Machines Corporation, Shelley M Beckstrand, June 18, 2002: US06408341 (42 worldwide citation)

A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs mes ...


5
James William Feeney, Howard Thomas Olnowich, George William Wilhelm Jr: Method and apparatus for maintaining message order in multi-user FIFO stacks. International Business Machines Corporation, Shelley M Beckstrand, May 4, 1999: US05901291 (15 worldwide citation)

A digital parallel processing system wherein a plurality of nodes communicate via messages sent over an interconnection network. Messages are maintained in strict chronological order even though sent by nodes where several sources are generating messages simultaneously. A network adapter is describe ...


6
Howard Thomas Olnowich, Michael Wayland Dotson, James William Feeney, Michael Hans Fisher, John David Jabusch, Robert Francis Lusch, Michael Anthony Maniguet: Apparatus for adapting message protocols for a switch network and a bus. International Business Machines Corporation, Michele A Jenkens & Gilchrist Mobley, Richard M Goldman, April 21, 1998: US05742761 (13 worldwide citation)

A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functio ...


7
James William Feeney, John David Jabusch, Robert Francis Lusch, Howard Thomas Olnowich: Selectable checking of message destinations in a switched parallel network. International Business Machines Corporation, Eugene I Shkurko, Shelley M Beckstrand, July 28, 1998: US05786771 (10 worldwide citation)

A method and hardware apparatus provide a fault tolerant and flexible multi-stage network addressing scheme for transmitting a message with a header containing control bits for selecting from various destination checking functions to be performed. Upon arrival of the message at a node, destination c ...


8
Raymond J Eberhard, James William Feeney: Low power access to a computing unit from an external source. International Business Machines Corporation, Kevin P Radigan, Arthur J Samodovitz, July 26, 2005: US06922788 (8 worldwide citation)

A method for conserving energy in a computing unit and transferring data between the computing unit and an external source. The computing unit is in a power saving mode. The method includes receiving at the computing unit a request from an external source, determining which components of the computi ...


9
Howard Thomas Olnowich, Michael Wayland Dotson, James William Feeney, Robert Francis Lusch, Michael Anthony Maniguet: Automatic hardware message header generator. International Business Machines Corporation, David L Adour, Eugene I Shkurko, Shelley M Beckstrand, July 13, 1999: US05922063 (7 worldwide citation)

A method and apparatus for reducing the software overhead of message passing in parallel systems. Special purpose hardware assists in constructing each data message sent through a network. Message passing systems generally require that every message be prefixed with a message header describing the k ...


10
James William Feeney, Jorge R Rodriquez, Edward Stanley Suffern, Robert William Bartoldus: Dynamic preamble configuration on a shared bus. International Business Machines Corporation, Bracewell & Patterson, May 11, 2004: US06735635 (5 worldwide citation)

A method and system for adjusting a message preamble on a shared bus, wherein the message preamble includes N synchronization characters, and each of the synchronization characters is separated in time by a random delay interval. First, an activity status is determined for the shared bus in terms of ...