1
James W Keeley, Thomas F Joyce: Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization. Honeywell Information Systems, Faith F Driscoll, John S Solakian, September 22, 1987: US04695943 (84 worldwide citation)

A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their o ...


2
George J Barlow, James W Keeley: Resilient bus system. Honeywell Bull, Faith F Driscoll, John S Solakian, August 16, 1988: US04764862 (68 worldwide citation)

A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units ...


3
George J Barlow, James W Keeley: Resilient bus system. Honeywell Bull, Faith F Driscoll, John S Solakian, August 9, 1988: US04763243 (64 worldwide citation)

A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units ...


4
George J Barlow, James W Keeley, Richard A Lemay, Jian Kuo Shen, Robert V Ledoux deceased, Thomas F Joyce, Richard P Kelly, Robert C Miller: Recovery method and apparatus for a pipelined processing unit of a multiprocessor system. Bull HN Information Systems, Faith F Driscoll, John S Solakian, March 9, 1993: US05193181 (61 worldwide citation)

The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and assoc ...


5
James W Keeley: Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement. Honeywell Bull, Faith F Driscoll, John S Solakian, November 15, 1988: US04785395 (54 worldwide citation)

A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units. For completely independent operation, each processing unit is allocated one-half of the total available cache memory space by separ ...


6
James W Keeley: Shared interface apparatus for testing the memory sections of a cache unit. Honeywell Information Systems, Faith F Driscoll, John S Solakian, March 11, 1986: US04575792 (52 worldwide citation)

The circuits of a cache unit constructed from a single board are divided into a cache memory section and a controller section. The cache unit is connectable to the central processing unit (CPU) of a data processing system through the interface circuits of the controller section. Test mode logic circ ...


7
James W Keeley, Edwin P Fisher, John L Curley: Multilevel cache system with graceful degradation capability. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, August 7, 1984: US04464717 (48 worldwide citation)

The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting ...


8
James W Keeley, George J Barlow: Read in process memory apparatus. Honeywell Bull, Faith F Driscoll, John S Solakian, August 30, 1988: US04768148 (43 worldwide citation)

A cache memory subsystem couples to main memory through interface circuits via a system bus in common with a plurality of central processing subsystems which have similar interface circuits. The cache memory subsystem includes multilevel directory memory and buffer memory pipeline stages shareable b ...


9
George J Barlow, James W Keeley, Chester M Nibby Jr: Cache resiliency in processing a variety of address faults. Bull HN Information Systems, Faith F Driscoll, John S Solakian, May 23, 1989: US04833601 (42 worldwide citation)

A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsyst ...


10
George J Barlow, Elmer W Carroll, James W Keeley, Wallace A Martland, Victor M Morganti, Arthur Peters, Richard C Zelley: Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing. Bull HN Information Systems, Gary D Clapp, John S Solakian, December 28, 1993: US05274797 (41 worldwide citation)

A data processing unit includes a number of tightly coupled central subsystems, a number of peripheral subsystems, a main memory and a system management facility all coupled in common to a system bus. The system management unit has top priority on the system bus and includes centralized resources wh ...