1
James W Adkisson, John A Bracchitta, John J Ellis Monaghan, Jerome B Lasky, Effendi Leobandung, Kirk D Peterson, Jed H Rankin: Double planar gated SOI MOSFET structure. International Business Machines Corporation, Michael E Whitham, Eugene I Shkurko, Mark F Chadurjian, November 19, 2002: US06483156 (132 worldwide citation)

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by ...


2
James W Adkisson, Ramachandra Divakaruni, Jeffrey P Gambino, Jack A Mandelman: Embedded DRAM on silicon-on-insulator substrate. International Business Machines Corporation, William D Sabo, Schmeiser Olsen & Watts, February 26, 2002: US06350653 (132 worldwide citation)

A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used ...


3
James W Adkisson, Ramachandra Divakaruni, Jeffrey P Gambino, Jack A Mandelman: Semiconductor device of an embedded DRAM on SOI substrate. International Business Machines Corporation, William D Sabo, Schmeiser Olsen & Watts, July 8, 2003: US06590259 (131 worldwide citation)

A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used ...


4
James W Adkisson, Arne W Ballantine, Ramachandra Divakaruni, Jeffrey B Johnson, Erin C Jones, Hon Sum P Wong: Method for making multiple threshold voltage FET using multiple work-function gate materials. International Business Machines Corporation, Robert Curcio, Richard A Henkler, DeLio & Peterson, September 28, 2004: US06797553 (98 worldwide citation)

A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pat ...


5
James W Adkisson, Paul D Agnello, Arne W Ballantine, Rama Divakaruni, Erin C Jones, Jed H Rankin: Double gate trench transistor. International Business Machines Corporation, Mark F Chadurjian, Whitham Curtis & Christofferson P C, October 29, 2002: US06472258 (94 worldwide citation)

A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is ...


6
James W Adkisson, Michael Caterer, James T Marsh, Hung Ng, James M Oberschmidt, Jed H Rankin: Process for defining a pattern using an anti-reflective coating and structure therefor. International Business Machines Corporation, William D Sabo, Pollock Vande Sande & Amernick, February 29, 2000: US06030541 (53 worldwide citation)

A pattern in a surface is defined by providing on the surface a hard mask material; depositing an anti-reflective coating on the hard mask material; applying a photoresist layer on the anti-reflective coating; patterning the photoresist layer, anti-reflective layer and hard mask material; and removi ...


7
James W Adkisson, Jeffrey P Gambino, Zhong Xiang He, Mark D Jaffe, Robert K Leidy, Stephen E Luce, Richard J Rassel, Edmund J Sprogis: CMOS imager array with recessed dielectric. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Richard M Kotulak Esq, August 24, 2010: US07781781 (42 worldwide citation)

A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel diele ...


8
James W Adkisson, David W Davis, Paul A Ishman: High speed printer with multiple paper paths. Florida Data Corporation, Howard L Rose, June 5, 1984: US04452543 (39 worldwide citation)

A high speed printer has multiple paths to accommodate cut paper sheets, manually fed paper and continuous forms for supply to a cylindrical platen such that the printer can be utilized with various types and sizes of paper. The printer includes a bail mechanism operable to capture the cut paper she ...


9
James W Adkisson, Jeffrey P Gambino, Mark D Jaffe, Robert K Leidy, Anthony K Stamper: Damascene copper wiring image sensor. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Anthony J Canale, March 20, 2007: US07193289 (38 worldwide citation)

An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, ...


10
James W Adkisson, Greg Bazan, John M Cohn, Matthew S Grady, Thomas G Sopchak, David P Vallett: Method of adding fabrication monitors to integrated circuit chips. International Business Machines Corporation, Schmeiser Olsen & Watts, Richard M Kotulak, July 3, 2007: US07240322 (31 worldwide citation)

An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circ ...