1
James Rathburn: Compliant conductive nano-particle electrical interconnect. HSIO Technologies, Stoel Rives, September 3, 2013: US08525346 (46 worldwide citation)

An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is loca ...


2
James Rathburn: Selective metalization of electrical connector or socket housing. Hsio Technologies, Stoel Rives, June 24, 2014: US08758067 (45 worldwide citation)

A electrical interconnect adapted to provide an interface between contact pads on an IC device and a PCB. The electrical interconnect includes a multi-layered substrate with a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second op ...


3
James Rathburn: Compliant printed circuit semiconductor package. HSIO Technologies, Stoel Rives, December 31, 2013: US08618649 (43 worldwide citation)

A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed i ...


4
James Rathburn: Compliant core peripheral lead semiconductor test socket. Hsio Technologies, Stoel Rives, December 17, 2013: US08610265 (43 worldwide citation)

An electrical interconnect for providing a temporary interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the I ...


5
James Rathburn: Compliant core peripheral lead semiconductor socket. Hsio Technologies, Stoel Rives, September 9, 2014: US08829671 (38 worldwide citation)

An electrical interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is locat ...


6
James Rathburn: Method of making a compliant printed circuit peripheral lead semiconductor test socket. HSIO Technologies, Stoel Rives, July 29, 2014: US08789272 (37 worldwide citation)

A test socket that provides a temporary interconnect between terminals on an integrated circuit (IC) device and contact pads on a test printed circuit board (PCB). The test socket includes a compliant printed circuit and a socket housing. The compliant printed circuit includes at least one compliant ...


7
James Rathburn: High performance surface mount electrical interconnect. Hsio Technologies, Stoel Rives, February 17, 2015: US08955215 (29 worldwide citation)

A method of forming an interconnect assembly including forming a substrate with a plurality of through holes extending from a first major surface to a second major surface. A plurality of recesses are formed in the second major surface of the substrate that at least partially overlap with the plural ...


8
James Rathburn: Bumped semiconductor wafer or die level electrical interconnect. Hsio Technologies, Stoel Rives, March 24, 2015: US08988093 (29 worldwide citation)

A probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a sh ...


9
James Rathburn: Copper pillar full metal via electrical circuit structure. HSIO Technologies, Stoel Rives, March 24, 2015: US08987886 (29 worldwide citation)

An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is deposited in a plurality of the fi ...


10
James Rathburn: Singulated semiconductor device separable electrical interconnect. Hsio Technologies, Stoel Rives, March 24, 2015: US08984748 (28 worldwide citation)

A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned rela ...