1
Mark G Johnson, Thomas H Lee, Vivek Subramanian, Paul Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, March 7, 2000: US06034882 (945 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. ...


2
Mark G Johnson, Thomas H Lee, Vivek Subramanian, P Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, February 6, 2001: US06185122 (505 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for cont ...


3
Mark G Johnson, Thomas H Lee, Vivek Subramanian, Paul Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Brinks Hoffer Gilson & Lione, November 19, 2002: US06483736 (294 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for cont ...


4
Mark G Johnson, Thomas H Lee, Vivek Subramanian, P Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, February 26, 2002: US06351406 (287 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for cont ...


5
Calvin K Li, N Johan Knall, Michael A Vyvoda, James M Cleeves, Vivek Subramanian: Patterning three dimensional structures. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, September 30, 2003: US06627530 (283 worldwide citation)

The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration between a first signal line and a second signal li ...


6
Thomas H Lee, Vivek Subramanian, James M Cleeves, Andrew J Walker, Christopher J Petti, Igor G Kouznetzov, Mark G Johnson, Paul Michael Farmwald, Brad Herner: Monolithic three dimensional array of charge storage devices containing a planarized surface. Matrix Semiconductor, Foley & Lardner, April 19, 2005: US06881994 (250 worldwide citation)

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.


7
James M Cleeves: Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays. Matrix Semiconductor, Zagorin O′ Brien & Graham, June 18, 2002: US06407953 (165 worldwide citation)

In a preferred integrated circuit embodiment, a write-once memory array includes at least one test bit line which provides a respective test memory cell at the far end of each respective word line relative to its word line driver, and further includes at least one test word line which provides a res ...


8
James M Cleeves: Three-dimensional memory. Sandisk 3D, July 25, 2006: US07081377 (153 worldwide citation)

A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.


9
Thomas H Lee, Vivek Subramanian, James M Cleeves, Andrew J Walker, Christopher Petti, Igor G Kouznetzov, Mark G Johnson, Paul M Farmwald, Brad Herner: Dense arrays and charge storage devices. Sandisk 3D, Foley & Lardner, October 31, 2006: US07129538 (133 worldwide citation)

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.


10
James M Cleeves, Vivek Subramanian: Multigate semiconductor device with vertical channel current and method of fabrication. Matrix Semiconductor, Foley & Lardner, January 13, 2004: US06677204 (127 worldwide citation)

The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage med ...