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James M Brayton, Michael W Rhodehamel, Nitin V Sarangdhar, Glenn J Hinton: Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 22, 1997: US05623628 (137 worldwide citation)

A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate t ...


2
Matthew A Fisch, James M Brayton, Ajay Malhotra: Method and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteed. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 9, 1996: US05535345 (26 worldwide citation)

In accordance with the preferred embodiment of the present invention, a bus interface unit of a microprocessor is provided with a Micro Request Sequencer (EBMRS) disposed between a bus scheduling queue (EBBQ) and external bus control logic (EBCTL). Under normal bus request traffic, the EBMRS is effe ...


3
Nitin V Sarangdhar, Wen Han Wang, Michael W Rhodehamel, James M Brayton, Amit Merchant, Matthew A Fisch: Computer system that maintains system wide cache coherency during deferred communication transactions. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 28, 1997: US05682516 (26 worldwide citation)

A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete t ...


4
Nitin V Sarangdhar, Michael W Rhodehamel, Amit A Merchant, Matthew A Fisch, James M Brayton: Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 5, 1996: US05572702 (18 worldwide citation)

Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be sati ...


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Michael W Rhodehamel, Nitin V Sarangdhar, Amit A Merchant, Matthew A Fisch, James M Brayton: Method and apparatus for self-snooping a bus during a boundary transaction. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 18, 1998: US05797026 (15 worldwide citation)

A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O ...


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Nitin V Sarangdhar, Michael W Rhodehamel, Amit A Merchant, Matthew A Fisch, James M Brayton: Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency. Intel Corporation, Seth Kalson, June 1, 1999: US05909699 (8 worldwide citation)

Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be sati ...


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