1
Ashok Challa, Alan Elbanhawy, Dean E Probst, Steven P Sapp, Peter H Wilson, Babak S Sani, Becky Losee, Robert Herrick, James J Murphy, Gordon K Madson, Bruce D Marchant, Christopher B Kocon, Debra S Woolsey: Methods of making power semiconductor devices with thick bottom oxide layer. Fairchild Semiconductor Corporation, Kilpatrick Townsend & Stockton, March 27, 2012: US08143124 (110 worldwide citation)

A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a char ...


2
James J Murphy, Janos Farkas, Lucia C Markert, Rahul Jairath: Point of use slurry dispensing system. National Semiconductor, Sematech, AT&T GIS, William W Kidd, December 26, 1995: US05478435 (78 worldwide citation)

A point of use slurry dispensing system with controls for dilution, temperature and oxidizer/etchant/additive infusion. A slurry in unmixed form and a diluting agent are independently pumped to a pad on a CMP tool. Liquid heaters are used to heat the slurry and the diluting agent to a desirable temp ...


3
James J Murphy: Selective oxide deposition in the bottom of a trench. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, September 3, 2002: US06444528 (42 worldwide citation)

A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom ...


4
Henry W Hurst, James J Murphy: Method for creating thick oxide on the bottom surface of a trench structure in silicon. Fairchild Semiconductor Corporation, Babak S Sani, Townsend and Townsend and Crew, August 20, 2002: US06437386 (37 worldwide citation)

A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom ...


5
Henry W Hurst, James J Murphy: Method for creating thick oxide on the bottom surface of a trench structure in silicon. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, March 1, 2005: US06861296 (16 worldwide citation)

A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom ...


6
James Pan, James J Murphy: Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein. Fairchild Semiconductor Corporation, Kilpatrick Townsend & Stockton, May 3, 2011: US07936009 (10 worldwide citation)

A shielded gate trench field effect transistor (FET) comprises trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench. The shield electrode is insulated from the semiconductor region by a shield dielectric. A gate electrode is disposed in ea ...


7
James J Murphy: Patterned metallized film and method for making same. American Decal & Manufacturing Company, Arnold White & Durkee, October 8, 1991: US05055343 (7 worldwide citation)

A patterned metallized film comprises a transparent or translucent polymeric film coated on one side with a thin coating of metal, with the metal coating and the polymeric film being bonded to each other. The metal coating has a multiplicity of fractures of different sizes distributed throughout the ...


8
Hamza Yilmaz, Steven Sapp, Qi Wang, Minhua Li, James J Murphy, John Robert Diroll: Semiconductor die packages using thin dies and metal substrates. Fairchild Semiconductor Corporation, Towsend and Townsend and Crew, August 3, 2010: US07768075 (4 worldwide citation)

A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is a ...


9
Michael D Gruenhagen, Suku Kim, James J Murphy, Ihsiu Ho, Eddy Tjhia, Chung Lin Wu, Mark Larsen, Rohit Dikshit: Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same. Fairchild Semiconductor Corporation, Kilpatrick Townsend & Stockton, November 15, 2011: US08058732 (4 worldwide citation)

Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodime ...


10
Michael D Gruenhagen, Suku Kim, James J Murphy, Eddy Tjhia, Chung Lin Wu, Mark Larsen, Douglas E Dolan: Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same. Fairchild Semiconductor Corporation, Kenneth E Horton, Kirton McConkie, December 3, 2013: US08598035 (2 worldwide citation)

Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on ...