1
James D Guilford, William R Wheeler, Matthew J Adiletta, Daniel Cutter: Journaling for parallel hardware threads in multithreaded processor. Intel Corporation, Fish & Richardson P C, December 30, 2003: US06671827 (65 worldwide citation)

A method of debugging code that executes in a multithreaded processor having microengines includes receiving a journal write command and an identification representing a selected one of the microengines from a remote user interface connected to the processor, pausing program execution in the threads ...


2
Donald F Hooper, Desmond R Johnson, James D Guilford, Richard D Muratori: Hop method for stepping parallel hardware threads. Intel Corporation, Fish & Richardson P C, September 13, 2005: US06944850 (38 worldwide citation)

A method of debugging software that executes in a multithreaded processor having a plurality of microengines includes pausing program execution in threads of execution within a target microengine, inserting a segment of executable code into an unused section of the target microengine's microstore, e ...


3
Debra Bernstein, Serge Kornfeld, Desmond R Johnson, Donald F Hooper, James D Guilford, Richard D Muratori: Breakpoint method for parallel hardware threads in multithreaded processor. Intel Corporation, Fish & Richardson P C, March 28, 2006: US07020871 (36 worldwide citation)

A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads ...


4
Vinodh Gopal, Gilbert M Wolrich, Erdinc Ozturk, James D Guilford, Kirk S Yap, Sean M Gulley, Wajdi K Feghali, Martin G Dixon: SIMD integer multiply-accumulate instruction for multi-precision arithmetic. Intel Corporation, Nicholson De Vos Webster & Elliot, January 12, 2016: US09235414 (25 worldwide citation)

A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register ...


5
Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, John Sweeney, James D Guilford: Free list and ring data structure management. Intel Corporation, Fish & Richardson P C, February 26, 2008: US07337275 (9 worldwide citation)

A method of managing a free list and ring data structure, which may be used to store journaling information, by storing and modifying information describing a structure of the free list or ring data structure in a cache memory that may also be used to store information describing a structure of a qu ...


6
Desmond R Johnson, Donald F Hooper, James D Guilford: Multiple image dynamic bind and load procedure for a multi-processor. Intel Corporation, Fish & Richardson P C, January 27, 2004: US06684395 (9 worldwide citation)

A method and mechanism for executing an application by a processor in a multi-processor configuration of processors, each having an associated instruction memory is presented. The application receives object code that includes an image for at least one other processor in the multi-processor configur ...


7
Gilbert M Wolrich, Kirk S Yap, James D Guilford, Vinodh Gopal, Sean M Gulley: Instruction set for message scheduling of SHA256 algorithm. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 16, 2014: US08838997 (7 worldwide citation)

A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message in ...


8
Vinodh Gopal, James D Guilford, Sudhir K Satpathy, Sanu K Mathew: Methods and apparatus to parallelize data decompression. Intel Corporation, Hanley Flight & Zimmerman, November 1, 2016: US09484954 (6 worldwide citation)

Methods and apparatus to parallelize data decompression are disclosed. A method selects the initial starting positions in a compressed data bitstream. A first one of the initial starting positions is adjusted to determine a first adjusted starting position by decoding the bitstream starting at a tra ...


9
James D Guilford: Debug system having assembler correcting register allocation errors. Intel Corporation, Daly Crowley Mofford & Durkee, January 13, 2009: US07478374 (4 worldwide citation)

An assembler, which can be provided as part of a debugger and/or development system, avoids register allocation errors, such as register bank conflicts and/or insufficient physical registers, automatically.


10
Vinodh Gopal, Erdinc Ozturk, James D Guilford, Gilbert M Wolrich: Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction. Intel Corporation, Nicholson De Vos Webster & Elliott, March 22, 2016: US09292297 (4 worldwide citation)

According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to ...