1
Yoav Talgam, James A Klingshirn, James B Gullette: Cache which provides status information. Motorola, James L Clingan Jr, November 19, 1991: US05067078 (45 worldwide citation)

A first processing system is coupled to a plurality of integrated circuits along a P bus. Each of these integrated circuits has a combination cache and memory management unit (MMU). The cache/MMU integrated circuits are also connected to a main memory via an M bus. A second processing system is also ...


2
James B Gullette, William C Moyer, Michael J Garcia: Method and apparatus for performing a snoop-retry protocol in a data processing system. Motorola, Charlotte B Whitaker, April 9, 1996: US05506971 (44 worldwide citation)

A data processing system (10) and method for performing a snoop-retry protocol using an arbiter (14). Multiple bus masters (12, 16, 17) are coupled to multiple shared buses (20, 22, 24, 26). Each bus master (12, 16, 17) may initiate a bus transaction ("initiating master"), or snoop the bus transacti ...


3
William C Moyer, James B Gullette, Michael J Garcia: Method and apparatus for performing bus arbitration in a data processing system. Motorola, Charlotte B Whitaker, May 16, 1995: US05416910 (43 worldwide citation)

A data processing system (10) and method for performing bus arbitration protocol using an arbiter (14). The data processing system (10) has multiple bus masters (12, 16) each of which is coupled to multiple shared buses (20, 22, 24, 28). The arbiter (14) detects a bus request from a requesting bus m ...


4
William C Moyer, James B Gullette, Kara B Pepe: System for executing a plurality of tasks within an instruction in different orders depending upon a conditional value. Motorola, Susan C Hill, January 14, 1997: US05594880 (17 worldwide citation)

A method and apparatus for determining instruction execution ordering in a data processing system (10). In one form, a control bit (52) is used by data processing system (10) to determine whether a standard instruction or a modified instruction is executed. The standard instruction performs a read b ...


5
James B Gullette: Methods for analyzing cells of a cell library. GlobalFoundries, Ingrassia Fisher & Lorenz P C, May 13, 2014: US08726217 (9 worldwide citation)

Methods and systems are provided for analyzing cells of a cell library used to generate a layout. One exemplary method involves determining a routed connection location utilized in the layout for a pin of the cell for each instance of the cell in the layout. The method continues by determining a uti ...


6
Marc Tarabbia, James B Gullette, Mahbub Rashed, David S Doman, Irene Y Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung Hyun Rhee, Jason E Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan: Semiconductor device having contact layer providing electrical connections. GLOBALFOUNDRIES, Ingrassia Fisher & Lorenz P C, December 3, 2013: US08598633 (1 worldwide citation)

A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the cont ...


7
James B GULLETTE: Methods for analyzing cells of a cell library. Globalfoundries, July 26, 2012: US20120192135-A1

Methods and systems are provided for analyzing cells of a cell library used to generate a layout. One exemplary method involves determining a routed connection location utilized in the layout for a pin of the cell for each instance of the cell in the layout. The method continues by determining a uti ...