1
James Allan Kahle, Albert J Loper, Soummya Mallick, Aubrey Deene Ogden, John Victor Sell: Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization. International Business Machines Corporation, Andrew J Dillon, June 9, 1998: US05764969 (98 worldwide citation)

A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execu ...


2
David John Craft, Pradeep K Dubey, Harm Peter Hofstee, James Allan Kahle: Method and system for controlled distribution of application code and content data within a computer network. International Business Machines Corporation, Casimer K Salys, Jack V Musgrove, October 13, 2009: US07603703 (67 worldwide citation)

A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client fo ...


3
David John Craft, Pradeep K Dubey, Harm Peter Hofstee, James Allan Kahle: Method and system for controlled distribution of application code and content data within a computer network. International Business Machines Corporation, Libby Z Handelsman, Jack V Musgrove, January 19, 2010: US07650491 (65 worldwide citation)

A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client fo ...


4
Cang Ngoc Tran, James Allan Kahle: Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access. International Business Machines Corporation, Anthony V S England, Andrew J Dillon, May 4, 1999: US05901294 (64 worldwide citation)

A method and system for enhanced bus arbitration in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-bu ...


5
James Allan Kahle, Michael John Mayfield, Francis Patrick O&apos Connell, David Scott Ray, Edward John Silha, Joel M Tendler: Software prefetch system and method for predetermining amount of streamed data. International Business Machines Corporation, Kelly K Kordzik, Casimer K Salys, Winstead Sechrest & Minick P C, June 3, 2003: US06574712 (63 worldwide citation)

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetc ...


6
James Allan Kahle, Charles Roberts Moore: Partitioned issue queue and allocation strategy. International Business Machines Corporation, Joseph P Lally, Volel Emile, Thomas E Tyson, April 27, 2004: US06728866 (53 worldwide citation)

A microprocessor and method of processing instructions for addressing timing assymetries are disclosed. A sequence of instructions including a first instruction and a second instruction are received. Dependency logic determines if any dependencies between the first and second instructions. The depen ...


7
James Allan Kahle, Alexander Erik Mericas, Kevin Franklin Reick, Joel M Tendler: System and method for tracing. International Business Machines Corporation, Richard F Frankeny, Thomas E Tyson, Winstead Sechrest & Minick P C, March 25, 2003: US06539500 (48 worldwide citation)

The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by d ...


8
James Allan Kahle, Michael John Mayfield, Francis Patrick O&apos Connell, David Scott Ray, Edward John Silha, Joel Tendler: System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism. International Business Machines Corporation, Kelly K Kordzik, Casimer K Salys, Winstead Sechrest & Minick P C, October 1, 2002: US06460115 (47 worldwide citation)

A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of c ...


9
Cang Ngoc Tran, James Allan Kahle: Method and system for simultaneous variable-width bus access in a multiprocessor system. International Business Machines Corporation, Anthony V S England, Andrew J Dillon, June 15, 1999: US05913044 (45 worldwide citation)

A method and system for enhanced bus access in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses m ...


10
Michael Stephen Floyd, James Allan Kahle, Hung Qui Le, John Anthony Moore, Kevin Franklin Reick, Edward John Silha: Method and apparatus for patching problematic instructions in a microprocessor using software interrupts. International Business Machines Corporation, Duke W Yee, Thomas E Tyson, Stephen J Walder Jr, October 7, 2003: US06631463 (43 worldwide citation)

A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The matc ...