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James A Farrell, Richard L Sites: Configurable set associative cache with decoded data element enable lines. Digital Equipment Corporation, Cesari and McKenna, May 7, 1991: US05014195 (89 worldwide citation)

A set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag comparators corresponding to the maximum possible number of sets, a data element select logic circuit, and ...


2
Thomas B Brightman, Andrew T Brown, John F Brown, James A Farrell, Andrew D Funk, David J Husak, Edward J McLellan, Mark A Sankey, Paul Schmitt, Donald A Priore: Digital communications processor. Freescale Semiconductor, Gordon E Nelson, August 29, 2006: US07100020 (52 worldwide citation)

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). T ...


3
James A Farrell, Bruce A Gieseke: Register scoreboard logic with register read availability signal to reduce instruction issue arbitration latency. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, December 26, 2000: US06167508 (15 worldwide citation)

Instruction issue logic is disclosed that assesses register availability. The issue logic comprises register scoreboard logic that includes destination register storage elements to identify destination registers of instructions queued for issue. An arbiter selects instructions for issue during a mac ...


4
James A Farrell, Bruce A Gieseke: Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, June 19, 2001: US06249855 (12 worldwide citation)

An arbiter system for the instruction issue logic of a CPU has at least two encoder circuits that select instructions in an instruction queue for issue to first and second execution units, respectively, based upon the positions of the instructions within the queue and requests by the instructions fo ...


5
Thomas B Brightman, Andrew D Funk, David J Husak, Edward J McLellan, Andrew T Brown, John F Brown, James A Farrell, Donald A Priore, Mark A Sankey, Paul Schmitt: High speed and high throughput digital communications processor with efficient cooperation between programmable processing components. Freescale Semiconductor, Gordon E Nelson, January 12, 2010: US07647472 (5 worldwide citation)

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). T ...


6
James A Farrell, Timothy C Fischer, Daniel L Leibholz, Bruce A Gieseke: Method for compacting an instruction queue. Hewlett Packard Development Company, March 9, 2004: US06704856 (5 worldwide citation)

A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor ...


7
James A Farrell, Timothy C Fischer, Daniel L Leibholz, Bruce A Gieseke: Method and apparatus for compacting a queue. Legal Department M S 35, May 20, 2004: US20040098566-A1

A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor ...


8
Thomas B Brightman, Andrew D Funk, David J Husak, Edward J McLellan, Andrew T Brown, John F Brown, James A Farrell, Donald A Priore, Mark A Sankey, Paul Schmitt: Digital communications processor. Gordon E Nelson Patent Attorney PC, December 28, 2006: US20060292292-A1

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). T ...


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