1
Jama I Barreh, Robert T Golla: Fetch speculation in a multithreaded processor. Sun Microsystems, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P c, February 27, 2007: US07185178 (55 worldwide citation)

In one embodiment, a processor comprises an instruction cache and a fetch generator circuit coupled thereto. The fetch generator circuit is configured to generate at least one fetch request to the instruction cache for at least one of the plurality of threads. The fetch generator circuit is also con ...


2
Jama I Barreh, Manish K Shah: Handling duplicate cache misses in a multithreaded/multi-core processor. Sun Microsystems, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, October 7, 2008: US07434000 (37 worldwide citation)

In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache miss unit is configured to initiate a cache fill of a cache line for the cache responsive to a first cache miss in the cache, wherein the first cache miss corresponds to a first thread of a plurali ...


3
Jama I Barreh, Manish K Shah: Cache error handling in a multithreaded/multi-core processor. Sun Microsystems, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, April 1, 2008: US07353445 (12 worldwide citation)

In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error detection unit is configured to detect an error in data output by the cache responsive to an access corre ...


4
Christopher H Olson, Paul J Jordan, Jama I Barreh: Processor and method providing instruction support for instructions that utilize multiple register windows. Oracle International Corporation, Meyertons Hood Kivlin Kowert & Goetzel P C, Anthony M Petro, October 8, 2013: US08555038 (11 worldwide citation)

A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction execution unit that, during operat ...


5
Jama I Barreh, Manish K Shah: Arbitrating cache misses in a multithreaded/multi-core processor. Oracle America, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, October 11, 2011: US08037250 (10 worldwide citation)

In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache is coupled to be accessed by cache accesses corresponding to a plurality of threads active in the processor. The cache miss unit is configured to record a plurality of cache misses detected in the ...


6
Robert T Golla, Paul J Jordan, Jama I Barreh: Delay slot handling in a processor. Oracle America, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, December 28, 2010: US07861063 (5 worldwide citation)

In one embodiment, a processor comprises a fetch unit and a pick unit. The fetch unit is configured to fetch instructions for execution by the processor. The pick unit is configured to schedule instructions fetched by the fetch unit for execution in the processor. The pick unit is configured to inhi ...


7
Robert T Golla, Jama I Barreh, Jeffrey S Brooks, Howard L Levy: Logical map table for detecting dependency conditions between instructions having varying width operand values. Oracle America, Meyertons Hood Kivlin Kowert & Goetzel P C, December 18, 2012: US08335912 (5 worldwide citation)

Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used to detect dependencies may be stored in a logical map table, which may include a content-addressable mem ...


8
Jama I Barreh, Manish Shah, Robert T Golla: Concurrent bypass to instruction buffers in a fine grain multithreaded processor. Sun Microsystems, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, June 3, 2008: US07383403 (4 worldwide citation)

In one embodiment, a processor comprises a plurality of instruction buffers, an instruction cache coupled to supply instructions to the plurality of instruction buffers, and a cache miss unit coupled to the instruction cache. Each of the plurality of instruction buffers is configured to store instru ...


9
Paul J Jordan, Robert T Golla, Jama I Barreh: Minimal address state in a fine grain multithreaded processor. Sun Microsystems, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, March 11, 2008: US07343474 (3 worldwide citation)

In one embodiment, a processor comprises a plurality of pipeline stages and a first circuit operable at a first pipeline stage of the plurality of pipeline stages. The first circuit is configured to maintain a plurality of program counters (PCs), each of which corresponds to one of a plurality of th ...


10
Robert T Golla, Yue Chang, Jama I Barreh: Hybrid instruction buffer. Oracle America, Robert C Kowert, Meyertons Hood Kivlin Kowert & Goetzel P C, July 17, 2012: US08225034 (2 worldwide citation)

In one embodiment, a storage buffer includes a plurality of storage locations configured to store a plurality of incoming instructions. The storage buffer also includes a shift FIFO that is coupled to the plurality of storage locations. The shift FIFO includes an entry configured to store an instruc ...