1
Hieu Van Tran, Jack Edward Frayer, William John Saiki, Michael Stephen Briner: Differential sense amplifier for multilevel non-volatile memory. Silicon Storage Technology, Gray Cary Ware & Freidenrich, April 26, 2005: US06885600 (44 worldwide citation)

A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high spe ...


2
Ya Fen Lin, Elbert Lin, Hieu Van Tran, Jack Edward Frayer, Bomy Chen: Word line voltage boosting circuit and a memory array incorporating same. Silicon Storage Technology, DLA Piper US, July 22, 2008: US07403418 (33 worldwide citation)

A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to ...


3
Hieu Van Tran, Jack Edward Frayer, William John Saiki, Michael Stephen Briner: High speed and high precision sensing for digital multilevel non-volatile memory system. Silicon Storage Technology, DLA Piper Rudnick Gray Cary US, May 2, 2006: US07038960 (21 worldwide citation)

A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high spe ...


4
Hieu Van Tran, William John Saiki, Jack Edward Frayer, Michael Stephen Briner: High voltage pulse method and apparatus for digital multilevel non-volatile memory integrated system. Silicon Storage Technology, Gray Cary Ware & Freidenrich, September 7, 2004: US06788608 (15 worldwide citation)

A digital multilevel non-volatile memory integrated system includes an apparatus and method for high voltage, high precision pulsing generation. A voltage generator includes a low voltage high speed generator, a low voltage to high voltage high speed level translator, and a high voltage driver. A pr ...


5
Bomy Chen, Douglas Lee, Jack Edward Frayer, Kai Man Yue: Integrated circuit with a reprogrammable nonvolatile switch for selectively connecting a source for a signal to a circuit. Silicon Storage Technology, Gray Cary Ware & Freidenrich, June 29, 2004: US06756632 (8 worldwide citation)

A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a floati ...


6
Jack Edward Frayer, Aaron Keith Olbrich, Paul Roger Stonelake, Anand Krishnamurthi Kulkarni, Yale Yueh Ma: Intelligent bit recovery for flash memory. Sandisk Enterprise IP, Morgan Lewis & Bockius, December 9, 2014: US08910020 (7 worldwide citation)

A method and system for intelligent bit recovery identifies toggling bits, which change in value from one read to the next, and examines a subset of potential bit patterns. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems t ...


7
Bomy Chen, Hieu Van Tran, Dana Lee, Jack Edward Frayer: Stacked gate memory cell with erase to gate, array, and method of manufacturing. Silicon Storage Technology, DLA Piper, October 21, 2008: US07439572 (7 worldwide citation)

A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injecton from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. F ...


8
Jack Edward Frayer, Vidyabhushan Mohan: Low-test memory stack for non-volatile storage. SanDisk Enterprise IP, Morgan Lewis & Bockius, March 10, 2015: US08976609 (5 worldwide citation)

The various embodiments described herein include systems, methods and/or devices used to packaging non-volatile memory. In one aspect, the method includes, selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which predefined die-level and sub-die level tests h ...


9
Jack Edward Frayer, Aaron K Olbrich: Systems, methods and devices for decoding codewords having multiple parity segments. SanDisk Enterprise IP, Morgan Lewis & Bockius, December 30, 2014: US08924815 (2 worldwide citation)

An error control decoding system decodes a codeword that includes a data word and two or more parity segments. The system includes a first decoder to decode the codeword by utilizing one or more first parity segments and the data word included in the codeword, and a second decoder to decode the code ...


10
Jack Edward Frayer: Nonvolatile memory device capable of simultaneous erase and program of different blocks. Silicon Storage Technology, DLA Piper Rudnick Gray Cary US, June 6, 2006: US07058754 (2 worldwide citation)

An integrated circuit memory device has a memory array which is partitioned into a plurality of blocks. Each block has an associated row decoder. Each block has a plurality of local bit lines connecting memory cells arranged in the same column. The row decoder is connected to a plurality of row line ...