1
Louis Lu Chen Hsu, Jack Allan Mandelman, Fariborz Assaderaghi: Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure. International Business Machines Corporation, Connolly Bove Lodge & Hutz, May 15, 2001: US06232173 (173 worldwide citation)

A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same substrate. An NVRAM cell structure. Processes for forming a memory structure that include ...


2
Roger Allen Booth Jr, Jack Allan Mandelman, William Robert Tonti: Semiconductor structures integrating damascene-body FinFETs and planar devices on a common substrate and methods for forming such semiconductor structures. International Business Machines Corporation, Wood Herron & Evans, April 1, 2008: US07352034 (105 worldwide citation)

Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are s ...


3
Jack Allan Mandelman, William Robert Tonti: Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates. International Business Machines Corporation, Wood Herron & Evans, October 19, 2010: US07818702 (90 worldwide citation)

Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on ...


4
Kangguo Cheng, Jack Allan Mandelman: Methods for forming semiconductor structures with buried isolation collars and semiconductor structures formed by these methods. International Business Machines Corporation, Wood Herron & Evans, October 12, 2010: US07811881 (79 worldwide citation)

A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried ...


5
Louis Lu Chen Hsu, Jack Allan Mandelman, Fariborz Assaderaghi: Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure. International Business Machines Corporation, Pollock Vande Sande & Amernick, March 9, 1999: US05880991 (76 worldwide citation)

A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same substrate. An NVRAM cell structure. Processes for forming a memory structure that include ...


6
Kangguo Cheng, Louis Lu Chen Hsu, Jack Allan Mandelman: Fin PIN diode. International Business Machines Corporation, Patterson & Sheridan, July 14, 2009: US07560784 (41 worldwide citation)

Embodiments of the invention generally relate to the field of semiconductor devices, and more specifically to fin-based junction diodes. A portion of a doped semiconductor fin may protrude through a first doped layer. An intrinsic layer may be disposed on the protruding semiconductor fin. A second s ...


7
Fariborz Assaderaghi, Louis Lu Chen Hsu, Jack Allan Mandelman: Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation. International Business Machines Corporation, Robert M Trepp, Anne Vachon Dougherty, September 19, 2000: US06121661 (37 worldwide citation)

Doped polysilicon plugs are formed in contact with MOSFET device regions and passing through the buried oxide region into the opposite type silicon substrate of an SOI structure. The polysilicon plugs are in contact with the sources and drains of the MOSFET devices to provide paths for dissipating p ...


8
Fariborz Assaderaghi, Louis Lu Chen Hsu, Jack Allan Mandelman: Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation. International Business Machines Corporation, Robert M Trepp, Anne Vachon Dougherty, March 5, 2002: US06352882 (37 worldwide citation)

Doped polysilicon plugs are formed in contact with MOSFET device regions and passing through the buried oxide region into the opposite type silicon substrate of an SOI structure. The polysilicon plugs are in contact with the sources and drains of the MOSFET devices to provide paths for dissipating p ...


9
Claude Louis Bertin, John Joseph Ellis Monaghan, Erik Leigh Hedberg, Terence Blackwell Hook, Jack Allan Mandelman, Edward Joseph Nowak, Wilbur David Pricer, Minh Ho Tong, William Robert Tonti: Switched body SOI (silicon on insulator) circuits and fabrication method therefor. International Business Machines Corporation, John J Goodwin, May 29, 2001: US06239649 (31 worldwide citation)

Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is co ...


10
Jack Oon Chu, Louis Lu Chen Hsu, Jack Allan Mandelman, Yuan Chen Sun, Yuan Taur: Vertical double-gate field effect transistor. International Business Machines Corporation, Susan M Murray, November 18, 1997: US05689127 (27 worldwide citation)

A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. ...



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