1
Xavier Baie
Bruce B Doris, Dureseti Chidambarrao, Xavier Baie, Jack A Mandelman, Devendra K Sadana, Dominic J Schepis: SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device. International Business Machines Corporation, Jay H Anderson, Whitham Curtis & Christofferson P C, April 6, 2004: US06717216 (146 worldwide citation)

Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET devices, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in ...


2
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, Jay H Anderson, Eugene I Shkurko, November 30, 2004: US06825529 (141 worldwide citation)

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


3
Xavier Baie
Bruce B Doris, Dureseti Chidambarrao, Xavier Baie, Jack A Mandelman, Devendra K Sadana, Dominic J Schepis: Field effect transistor with stressed channel and method for making same. International Business Machines Corporation, Whitham Curtis & Christofferson P C, Jay H Anderson, April 26, 2005: US06884667 (18 worldwide citation)

Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in ...


4
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, H Daniel Schnurmann, May 20, 2008: US07374987 (16 worldwide citation)

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


5
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, Dept 18g, February 24, 2005: US20050040460-A1

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


6
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, June 17, 2004: US20040113217-A1

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


7
Lawrence A Clevenger, Louis Lu Chen Hsu, Jack A Mandelman, Carl J Radens: Self-trimming method on looped patterns. International Business Machines Corporation, Richard M Ludwin Esq, McGinn & Gibb PLLC, October 14, 2003: US06632741 (213 worldwide citation)

A method of self-trimming pattern, includes forming a pattern containing a plurality of regular or irregular features within a first material deposited on a substrate, depositing a conformal layer of second material, and etching the second material to form spacers of the second material along the si ...


8
Ramachandra Divakauni, Mark C Hakey, William H L Ma, Jack A Mandelman, William R Tonti: SOI stacked DRAM logic. International Business Machines Corporation, Mark F Chadurjian, Whitman Curtis & Christofferson P C, April 8, 2003: US06544837 (202 worldwide citation)

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal ...


9
Fariborz Assaderaghi, Louis Lu Chen Hsu, Jack A Mandelman: Mixed memory integration with NVRAM, dram and sram cell structures on same substrate. International Business Machines Corporation, Joseph P Abate, July 23, 2002: US06424011 (195 worldwide citation)

A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same semiconductor on insulator substrate. An NVRAM cell structure. Processes for forming a mem ...


10
Carl J Radens, Gary B Bronner, Tze chiang Chen, Bijan Davari, Jack A Mandelman, Dan Moy, Devendra K Sadana, Ghavam Ghavami Shahidi, Scott R Stiffler: Silicon-on-insulator vertical array device trench capacitor DRAM. International Business Machines Corporation, H Daniel Schnurmann, May 20, 2003: US06566177 (164 worldwide citation)

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate ...



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