1
Brian Sze Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst: Field effect transistor and method of its manufacture. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, August 6, 2002: US06429481 (180 worldwide citation)

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each ...


2
Francois Hebert, Sze Hon Kwan, Izak Bencuya: Method of fabricating self-aligned contact trench DMOS transistors. National Semiconductor Corporation, Limbach & Limbach, October 22, 1996: US05567634 (132 worldwide citation)

A method of fabricating a trench DMOS transistor structure results in the contact to the transistor's source and body being self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distanc ...


3
Izak Bencuya: High voltage transistor having edge termination utilizing trench technology. Siliconix Incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, July 4, 1995: US05430324 (126 worldwide citation)

For a vertical DMOS power transistor or a high voltage bipolar transistor, an edge termination at the perimeter of the die surrounding the active transistor cells includes multiple spaced apart field rings. A trench is located between each adjacent pair of field rings and is insulated either by oxid ...


4
Izak Bencuya: Method for fabricating high voltage transistor having trenched termination. Siliconix Incorporated, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, February 25, 1997: US05605852 (106 worldwide citation)

For a vertical DMOS power transistor or a high voltage bipolar transistor, an edge termination at the perimeter of the die surrounding the active transistor cells includes multiple spaced apart field rings. A trench is located between each adjacent pair of field rings and is insulated either by oxid ...


5
Sze Hon Kwan, Izak Bencuya: Method of fabricating a self-aligned contact trench DMOS transistor structure. National Semiconductor Corporation, Limbach & Limbach L, September 9, 1997: US05665619 (98 worldwide citation)

A trench DMOS transistor structure includes a contact to the transistor's source and body that is self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges ...


6
Sze Hon Kwan, Izak Bencuya, Steven P Sapp: Self-aligned method of fabricating terrace gate DMOS transistor. National Semiconductor Corporation, Limbach & Limbach L, March 9, 1999: US05879994 (73 worldwide citation)

An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gate ...


7
Brian Sze Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst: Field effect transistor and method of its manufacture. Fairchild Semiconductor Corporation, Babak S Sani, Townsend and Townsend and Crew, March 23, 2004: US06710406 (38 worldwide citation)

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each ...


8
Hamza Yilmaz, Izak Bencuya: Closed cell transistor with built-in voltage clamp. Siliconix Incorporated, Skjerven Morrill MacPherson Franklin & Friel, August 4, 1992: US05136349 (38 worldwide citation)

A power transistor takes advantage of the lower breakdown voltage capability of a spherical junction. A clamping region having a spherical shape is provided in the gater region of an enclosed transistor cell. The clamping region has a lower breakdown voltage than do the active portions of the transi ...


9
Daniel Calafut, Izak Bencuya, Steven Sapp: Integrated zener diode protection structures and fabrication methods for DMOS power devices. National Semiconductor Corporation, Limbach & Limbach L, February 11, 1997: US05602046 (37 worldwide citation)

In one embodiment, modifications to the polysilicon gate, body, source, and contact masks of a DMOS process add a source-body monocrystalline gate protection diode under the gate pad by implanting an anode region beneath the gate. The anode is connected to the gate through the gate metal in the pad. ...


10
Izak Bencuya, Maria Christina B Estacio, Steven P Sapp, Consuelo N Tangpuz, Gilmore S Baje, Rey D Maligro: Low Resistance package for semiconductor devices. Fairchild Semiconductor Corporation, Townsend and Townsend and Crew, July 23, 2002: US06423623 (36 worldwide citation)

A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging ...