1
Richard W Jarvis, Iraj Emami, John L Nistler, Michael G McIntyre: Multipurpose defect test structure with switchable voltage contrast capability and method of use. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, October 2, 2001: US06297644 (89 worldwide citation)

A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than t ...


2
Richard W Jarvis, Iraj Emami, Charles E May: Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, September 17, 2002: US06452412 (87 worldwide citation)

A drop-in test structure fabricated upon a production integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology are described. The test structure may be fabricated upon an integrated circuit elevational pr ...


3
Thomas J Goodwin, Iraj Emami, Charles E May: Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control. Advanced Micro Devices, Williams Morgan & Amerson, May 6, 2003: US06560504 (35 worldwide citation)

A method is provided for manufacturing, the method including processing a workpiece in a processing step, detecting defect data after the processing of the workpiece in the processing step has begun and forming an output signal corresponding to at least one type of defect based on the defect data. T ...


4
Bhanwar Singh, Srikanteswara Dakshina Murthy, Khoi A Phan, Ramkumar Subramanian, Bharath Rangarajan, Iraj Emami: Real time immersion medium control using scatterometry. Advanced Micro Devices, Amin Turocy & Calvin, January 2, 2007: US07158896 (19 worldwide citation)

Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built u ...


5
Richard W Jarvis, Iraj Emami, Alan B Berezin: Semiconductor test structure with intentional partial defects and method of use. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, July 31, 2001: US06268717 (18 worldwide citation)

A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. A number of intentional partial defects may be formed at predetermined locations along the test structure. During irradiati ...


6
Thomas J Goodwin, Iraj Emami, Charles E May: Fractal filter applied to a contamination-free manufacturing signal to improve signal-to-noise ratios. Advanced Micro Devices, Williams Morgan & Amerson, June 5, 2001: US06242273 (10 worldwide citation)

A method is provided for manufacturing, the method including processing a workpiece in a processing step and detecting defect data after the processing of the workpiece in the processing step has begun. The method also includes filtering the defect data using a fractal filter and forming an output s ...


7
Richard W Jarvis, Iraj Emami, Charles E May: Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, September 25, 2001: US06294397 (5 worldwide citation)

A drop-in test structure fabricated upon a virtual integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology and integrated circuit fabrication equipment are described. According to an embodiment, the test ...


8
Bhanwar Singh, Qiaolin Zhang, Iraj Emami, Joyce S Oey Hewett, Luigi Capodiece: Optimizing critical dimension uniformity utilizing a resist bake plate simulator. Advanced Micro Devices, Amin Turocy & Calvin, February 19, 2008: US07334202 (4 worldwide citation)

A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A ...


9
Bhanwar Singh, Jason Phillip Cain, Harish Kumar Bolla, Iraj Emami: Scanner optimization for reduced across-chip performance variation through non-contact electrical metrology. Advanced Micro Devices, Amin Turocy & Calvin, December 2, 2008: US07460922 (3 worldwide citation)

The disclosed embodiments reduce across-chip performance variation through non-contact electrical metrology. According to a feature is a process control system that includes a component that measures transistor electrical performance in a product wafer. Also included in the system is a mapping compo ...


10
Bhanwar Singh, Khoi A Phan, Bharath Rangarajan, Iraj Emami, Ramkumar Subramanian: Composite alignment mark scheme for multi-layers in lithography. Advanced Micro Devices, Amin Turocy & Calvin, May 22, 2007: US07221060 (2 worldwide citation)

Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is a ...