1
Siva Ramakrishnan, Ioannis Schoinas: Performing memory RAS operations over a point-to-point interconnect. Intel Corporation, Rob D Anderson, October 24, 2006: US07127567 (67 worldwide citation)

In some embodiments, a memory transaction is received that was sent over an unordered interconnect. A determination is made as to whether an address conflict exists between the memory transaction and another memory transaction. If the address conflict exists the memory transaction is forwarded only ...


2
Ioannis Schoinas, Rajesh Madukkarumukumana, Gilbert Neiger, Richard Uhlig, Balaji Vembu: Caching support for direct memory access address translation. Intel Corporation, Philip A Pedigo, February 19, 2008: US07334107 (49 worldwide citation)

An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest d ...


3
Ioannis Schoinas, Rajesh Madukkarumakumana, Gilbert Neiger, Richard Uhlig, Ku jei King: Address translation for input/output devices using hierarchical translation tables. Intel Corporation, Grossman Tucker Perreault & Pfleger PLLC, October 28, 2008: US07444493 (44 worldwide citation)

An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O devi ...


4
Rajesh Madukkarumukumana, Ioannis Schoinas, Ku jei King, Balaji Vembu, Gilbert Neiger, Richard Uhlig: Fault processing for direct memory access address translation. Intel Corporation, Philip A Pedigo, March 4, 2008: US07340582 (41 worldwide citation)

An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address tran ...


5
Manoj Khare, Akhilesh Kumar, Ioannis Schoinas, Lily Pao Looi: Method and apparatus for managing transaction requests in a multi-node architecture. Intel Corporation, Sharmini N Green, November 29, 2005: US06971098 (39 worldwide citation)

Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received ordered group request belongs to a same ...


6
Rajesh S Madukkarumukumana, Ioannis Schoinas, Gilbert Neiger: Interrupt redirection for virtual partitioning. Intel Corporation, Thomas R Lane, May 22, 2007: US07222203 (37 worldwide citation)

The present disclosure relates to the handling of interrupts in a environment that utilizes virtual machines, and, more specifically, to the steering of interrupts between multiple logical processors running virtual machines.


7
Rajesh S Madukkarumukumana, Gilbert Neiger, Ioannis Schoinas: Resource partitioning and direct access utilizing hardware support for virtualization. Intel Corporation, Thomas R Lane, December 16, 2008: US07467381 (19 worldwide citation)

The present disclosure relates to the resource management of virtual machine(s) using hardware address mapping, and, more specifically, to facilitate direct access to devices from virtual machines, utilizing control of hardware address translation facilities.


8
Mani Ayyar, Ioannis Schoinas, Rama R Menon, Aniruddha Vaidya, Akhilesh Kumar: Conditional and vectored system management interrupts. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 7, 2008: US07433985 (17 worldwide citation)

An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. Th ...


9
Siva Ramakrishnan, Ioannis Schoinas: Synchronizing memory copy operations with memory accesses. Intel Corporation, Rob D Anderson, October 24, 2006: US07127566 (8 worldwide citation)

In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory addr ...


10
Eric Delano, Ioannis Schoinas, Akhilesh Kumar, Doddaballapur Narasimha Murthy Jayasimha: Band configuration agent for link based computing system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 6, 2008: US07370135 (2 worldwide citation)

A method is described that involves directing a configuration request through a switch core to a configuration agent. The method also involves processing the configuration request at the configuration agent. The method also involves sending a configuration command derived from the configuration requ ...