1
Mitsuyoshi Yamamoto, Ikuya Kawasaki, Hideo Inayoshi, Susumu Narita, Masaharu Kubo: Data processor and single-chip microcomputer with changing clock frequency and operating voltage. Hitachi, Antonelli Terry Stout & Kraus, July 7, 1998: US05778237 (207 worldwide citation)

A microcomputer has a clock generator capable of changing the frequency of an output clock signal: and a power circuit capable of changing the level of an operating voltage to be outputted. The frequencies of clock signals and the levels of operating voltages to be individually fed to a plurality of ...


2
Shinichi Yoshioka, Susumu Narita, Ikuya Kawasaki, Saneaki Tamaki: Processor with an addressable address translation buffer operative in associative and non-associative modes. Hitachi, Loudermille & Associates, November 10, 1998: US05835963 (59 worldwide citation)

A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in questi ...


3
Shigezumi Matsui, Mitsuyoshi Yamamoto, Shinichi Yoshioka, Susumu Narita, Ikuya Kawasaki, Susumu Kaneko, Kiyoshi Hasegawa: Microprocessor operating at high and low clok frequencies. Hitachi, Loudermilk & Associates, June 30, 1998: US05774701 (54 worldwide citation)

A microprocessor incorporating a PLL circuit using a clock pulse having a relatively low frequency as an input clock signal of a reference frequency to form an oscillating pulse of a relatively high frequency by multiplying the input clock signal. In the microprocessor, the operation of the PLL circ ...


4
Shinichi Yoshioka, Ikuya Kawasaki, Susumu Narita, Saneaki Tamaki: Data processor having an address translation buffer operable with variable page sizes. Hitachi, Alan R Loudermilk, August 18, 1998: US05796978 (43 worldwide citation)

A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses sh ...


5
Kazuhiko Iwasaki, Tsuneo Funabashi, Ikuya Kawasaki, Hideo Inayoshi, Atsushi Hasegawa, Takao Yaginuma, Eiki Kondoh: Data processing system with coprocessor. Hitachi, Hitachi Microcomputer Engineering, Hitachi Engineering, Antonelli Terry & Wands, January 16, 1990: US04894768 (34 worldwide citation)

When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus cycle is in the mode of transfer of the instruction to the coprocessor. In transferring an operand from t ...


6
Satoshi Masuda, Ikuya Kawasaki, Shigezumi Matsui: Software debugging system for writing a logical address conversion data into a trace memory of an emulator. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, September 4, 1990: US04954942 (31 worldwide citation)

The microprocessor has an address converting buffer to convert logical addresses into physical addresses and a signal generator representing the timing for the microprocessor to retrieve conversion information from an external memory and write it into the address converting buffer. With this configu ...


7
Satoshi Masuda, Ikuya Kawasaki, Shigezumi Matsui: System for logical address conversion data fetching from external storage and indication signal for indicating the information externally. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, January 11, 1994: US05278962 (30 worldwide citation)

The microprocessor has an address converting buffer to convert logical addresses into physical addresses and a signal generator representing the timing for the microprocessor to retrieve conversion information from an external memory and write it into the address converting buffer. With this configu ...


8
Shinichi Yoshioka, Ikuya Kawasaki, Susumu Narita, Saneaki Tamaki: Data processor for implementing virtual pages using a cache and register. Hitachi, Alan R Loudermilk, April 4, 2000: US06047354 (26 worldwide citation)

A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses sh ...


9
Kouzi Hashimoto, Atsushi Hasegawa, Ikuya Kawasaki, Kazuhiko Iwasaki: Microprocessor system. Hitachi, Hitachi Microcomputer Engineering, Antonelli Terry Stout & Kraus, March 9, 1993: US05193159 (25 worldwide citation)

When a coprocessor communicates a plurality of data items with a master processor and a memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with information indicating a data storage position as a data transfer source or destination. The mast ...


10
Makoto Hanawa, Ikuya Kawasaki, Tadahiko Nishimukai: Microprocessor for retrying data transfer. Hitachi, Antonelli Terry & Wands, July 4, 1989: US04845614 (25 worldwide citation)

A microprocessor and a peripheral equipment communicate data through a bus. If an error occurs during communication, the microprocessor starts the next bus cycle and commands retry of the data communication. If a predetermined number of times of retry fail, and if an address signal corresponds to an ...