1
Peter Z Onufryk, Jayesh Patel, Ihab Jaser, Ganesh T Seshan: Nonvolatile memory controller with host controller interface for retrieving and dispatching nonvolatile memory commands in a distributed manner. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, November 19, 2013: US08588228 (14 worldwide citation)

A nonvolatile memory controller includes a host controller interface, processors, a message networks and a data network. The host controller interface includes a command fetch module, command assembly buffers, and a command dispatch module. The command fetch module retrieves nonvolatile memory comma ...


2
Peter Z Onufryk, Jayesh Patel, Ihab Jaser: Interrupt technique for a nonvolatile memory controller. PMC Sierra, Kenneth Glass, Stanley J Pawlik, Glass & Associates, October 8, 2013: US08554968 (8 worldwide citation)

A nonvolatile memory controller processes a nonvolatile memory command and generates a completion status for the nonvolatile memory command. The nonvolatile memory controller transmits the completion status to a host processing unit for storage in a completion queue of the host processing unit. An i ...


3
Rino Micheloni, Peter Z Onufryk, Alessia Marelli, Christopher I W Norrie, Ihab Jaser: Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values. PMC SIERRA US, Glass & Associates, Kenneth Glass, Mark Peloquin, September 8, 2015: US09128858 (5 worldwide citation)

Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A ...


4
Rino Micheloni, Alessia Marelli, Peter Z Onufryk, Christopher I W Norrie, Ihab Jaser, Luca Crippa: System and method for accumulating soft information in LDPC decoding. Microsemi Storage Solutions, Glass & Associates, Kenneth Glass, September 27, 2016: US09454414 (3 worldwide citation)

A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft re ...


5
Rino Micheloni, Alessia Marelli, Peter Z Onufryk, Christopher I W Norrie, Ihab Jaser, Luca Crippa: System and method for higher quality log likelihood ratios in LDPC decoding. Microsemi Storage Solutions, Glass & Associates, Kenneth Glass, Molly Sauter, March 7, 2017: US09590656 (2 worldwide citation)

A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory ...


6
Rino Micheloni, Peter Z Onufryk, Alessia Marelli, Christopher I W Norrie, Ihab Jaser: Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system. PMC SIERRA US, Kenneth Glass, Mark Peloquin, Glass & Associates, July 28, 2015: US09092353 (2 worldwide citation)

Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the me ...


7
Rino Micheloni, Alessia Marelli, Peter Z Onufryk, Christopher I W Norrie, Ihab Jaser: Memory controller and integrated circuit device for correcting errors in data read from memory cells. Microsemi Storage Solutions, Glass & Associates, Kenneth Glass, Mark Peloquin, September 20, 2016: US09448881

An integrated circuit device for correcting errors in data read from memory cells includes a decoder, an encoder and a data management module. The data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing a code-ra ...


8
Mohammad Nikuie, Ihab Jaser: Apparatus and method for minimizing exclusive-OR (XOR) computation time. Microsemi Storage Solutions, Glass & Associates, Kenneth Glass, Mark Peloquin, October 25, 2016: US09477562

A line of data is read from a line of memory. Intended data is specified by a random location and a random size within the line of memory. The line of data is moved into temporary storage. The line of data and a zero are multiplexed using a control signal to output a line of adjusted data which is a ...