1
Ling Chen, Hung Cheng Sung, Chi Shiung Lo: Method for making self-aligned source/drain mask ROM memory cell using trench etched channel. Taiwan Semiconductor Manufacturing Company, George O Saile, Graham S Jones II, January 21, 1997: US05595927 (94 worldwide citation)

A device and a method are provided for manufacture of that semiconductor memory device on a silicon semiconductor substrate with a vertical channel. A dielectric layer pattern with openings through it is formed. Trenches are formed in the surface of the semiconductor substrate. The trenches have sid ...


2
Hung Cheng Sung, Ling Chen: Process for manufacturing a plug-diode mask ROM. Taiwan Semiconductor Manufacturing Company, George O Saile, Graham S Jones II, August 15, 1995: US05441907 (86 worldwide citation)

A method of manufacture of a Mask ROM on a semiconductor substrate comprises formation of a first plurality of conductor lines in a first array. A dielectric layer is formed upon the device with a matrix of openings therein in line with the first array. The openings expose the surface of the first c ...


3
Hung Cheng Sung, Ling Chen: Planarized plug-diode mask ROM structure. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Graham S Jones II, October 5, 1999: US05962903 (54 worldwide citation)

A Mask ROM and a method of manufacture of a Mask ROM on a semiconductor substrate comprises formation of a first plurality of conductor lines in a first array. A dielectric layer is formed upon the device with a matrix of openings therein in line with the first array. The openings expose the surface ...


4
Hung Cheng Sung, Ling Chen: Method of manufacturing metallic source line, self-aligned contact for flash memory devices. Taiwan Semiconductor Manufacturing Company, George O Saile, Graham S Jones II, May 20, 1997: US05631179 (41 worldwide citation)

Manufacture of an integrated circuit flash memory devices includes covering a semiconductor substrate with a tunnel oxide layer, a floating gate layer, an intergate dielectric layer, a control gate layer, a silicon dioxide dielectric layer over a silicon nitride layer. Then those layers over the tun ...


5
Hung Cheng Sung, Di Son Kuo, Chia Ta Hsieh, Yai Fen Lin: Poly tip formation and self-align source process for split-gate flash cell. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, September 12, 2000: US06117733 (32 worldwide citation)

A novel method of forming a first polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notch in two different ways in a nitride layer overlying the first polysilicon layer. In one embodiment, the notch ...


6
Chia Ta Hsieh, Hung Cheng Sung, Yai Fen Lin, Jack Yeh, Di Son Kuo: Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Sevgin Oktay, May 8, 2001: US06228695 (32 worldwide citation)

A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by ...


7
Chia Ta Hsieh, Yai Fen Lin, Di Son Kuo, Hung Cheng Sung, Jack Yeh: Method to increase coupling ratio of source to floating gate in split-gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, December 12, 2000: US06159801 (29 worldwide citation)

A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling w ...


8
Hung Cheng Sung, Ling Chen: Method of manufacturing self-aligned bit-line during EPROM fabrication. Taiwan Semiconductor Manufacturing Company, George O Saile, Graham S Jones II, December 31, 1996: US05589413 (24 worldwide citation)

An EPROM device is provided with self-aligned bit-lines. A tunnel oxide layer is formed on a semiconductor substrate. Blanket layers of doped, polysilicon layer, an interelectrode dielectric layer and a blanket polycide layer are formed over the dielectric layer. A TEOS dielectric layer is formed ov ...


9
Chia Ta Hsieh, Yai Fen Lin, Hung Cheng Sung, Chuang Ke Yeh, Di Son Kuo: Method of fabricating step poly to improve program speed in split gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, March 9, 1999: US05879992 (23 worldwide citation)

A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched t ...


10
Chia Ta Hsieh, Yai Fen Lin, Di Son Kuo, Hung Cheng Sung, Jack Yeh: Method to increase coupling ratio of source to floating gate in split-gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Sevgin Oktay, April 30, 2002: US06380583 (22 worldwide citation)

A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling w ...