1
Ross H Freeman, Hung Cheng Hsieh: Distributed memory architecture for a configurable logic array and method for using distributed memory. Xilinx, Edel M Young, Patrick T Bever, August 30, 1994: US05343406 (252 worldwide citation)

Additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array ...


2
Hung Cheng Hsieh, William S Carter, Charles S Erickson, Edmond Y Cheung: Logic structure and circuit for fast carry. November 30, 1993: US05267187 (119 worldwide citation)

Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function ...


3
Ross H Freeman, Hung Cheng Hsieh: Circuit for selecting a bit in a look-up table. Xilinx, Jeanette S Harms, January 30, 1996: US05488316 (117 worldwide citation)

This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other p ...


4
Hung Cheng Hsieh deceased, by William S Carter administrator, Charles R Erickson, Edmond Y Cheung: Logic structure and circuit for fast carry. Xilinx, Jeanette S Harms, Edel M Young, June 4, 1996: US05523963 (86 worldwide citation)

Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function ...


5
Hung Cheng Hsieh: 5-Transistor memory cell which can be reliably read and written. Xilinx Incorporated, Alan H MacPherson, Paul J Winters, Edel M Young, June 7, 1988: US04750155 (86 worldwide citation)

A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during r ...


6
Hung Cheng Hsieh: 5-transistor memory cell with known state on power-up. Xilinx Incorporated, Skjerven Morrill MacPherson Franklin & Friel, April 11, 1989: US04821233 (73 worldwide citation)

A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during r ...


7
Ross H Freeman, Hung Cheng Hsieh: Distributed memory architecture for a configurable logic array and method for using distribution memory. Xilinx, Edel M Young, July 11, 1995: US05432719 (62 worldwide citation)

This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other p ...


8
Hung Cheng Hsieh, William S Carter: Buffered routing element for a user programmable logic device. Xilinx, Skjerven Morrill MacPherson Franklin & Friel, August 8, 1989: US04855619 (50 worldwide citation)

A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at loctions within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangemen ...


9
Hung Cheng Hsieh: Power supply voltage level sensing circuit. Xilinx, Skjerven Morrill MacPherson Franklin & Friel, February 20, 1990: US04902910 (39 worldwide citation)

A power supply voltage level sensing circuit on an integrated circuit generates a reset signal that holds the components of the integrated circuit in a defined state when the power supply voltage level drops below a predetermined voltage. The reset signal is released when the power supply voltage le ...


10
Hung Cheng Hsieh: Memory cell with known state on power up. XILINX, Edel M Young, September 15, 1992: US05148390 (33 worldwide citation)

A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during r ...