1
Veeraraghavan S Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S Haran, Nicolas Loubet, Shom Ponoth, Stefan Schmitz, Theodorus E Standaert, Tenko Yamashita: Cut-very-last dual-epi flow. International Business Machines Corporation, Harrington & Smith, October 29, 2013: US08569152 (20 worldwide citation)

A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered por ...


2
Huiming Bu, Eduard A Cartier, Bruce B Doris, Young Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K Paruchuri, Michelle L Steen: CMOS transistors with differential oxygen content high-k dielectrics. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Vazken Alexanian, April 13, 2010: US07696036 (19 worldwide citation)

An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide sp ...


3
Veeraraghavan S Basker, Huiming Bu, Effendi Leobandung, Theodorus E Standaert, Tenko Yamashita, Chun Chen Yeh: SOI FinFET with recessed merged Fins and liner for enhanced stress coupling. International Business Machines Corporation, Cantor Colburn, Vazken Alexanian, May 21, 2013: US08445334 (15 worldwide citation)

FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the ...


4
Veeraraghavan S Basker, Andres Bryant, Huiming Bu, Wilfried Haensch, Effendi Leobandung, Chung Hsun Lin, Theodorus E Standaert, Tenko Yamashita, Chun chen Yeh: Method for fabricating finFET with merged fins and vertical silicide. International Business Machines Corporation, Stephen Bongini, Fleit Gibbons Gutman Bongini & Bianco PL, June 4, 2013: US08455313 (14 worldwide citation)

A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack incl ...


5
Veeraraghavan S Basker, Andres Bryant, Huiming Bu, Wilfried Haensch, Effendi Leobandung, Chung Hsun Lin, Theodorus E Standaert, Tenko Yamashita, Chun chen Yeh: finFET with merged fins and vertical silicide. International Business Machines Corporation, Stephen Bongini, Fleit Gibbons Gutman Bongini & Bianco PL, January 28, 2014: US08637931 (8 worldwide citation)

A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in th ...


6
Huiming Bu, Eduard A Cartier, Bruce B Doris, Young Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K Paruchuri, Michelle L Steen: CMOS transistors with differential oxygen content high-K dielectrics. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, October 11, 2011: US08035173 (8 worldwide citation)

An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide sp ...


7
Veeraraghavan S Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S Haran, Nicolas Loubet, Shom Ponoth, Stefan Schmitz, Theodorus E Standaert, Tenko Yamashita: Cut-very-last dual-EPI flow. International Business Machines Corporation, Harrington & Smith, November 26, 2013: US08592290 (6 worldwide citation)

A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered por ...


8
Huiming Bu, Satya N Chakravarti, Dechao Guo, Keith Kwong Hon Wong: Integration of passive device structures with metal gate layers. International Business Machines Corporation, Cantor Colburn, Vazken Alexanian, January 17, 2012: US08097520 (4 worldwide citation)

A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the ...


9
Takashi Ando, Huiming Bu, Ramachandra Divakaruni, Bruce B Doris, Chung Hsun Lin, Huiling Shang, Tenko Yamashita: Source-drain extension formation in replacement metal gate transistor device. International Business Machines Corporation, Harrington & Smith, November 26, 2013: US08592264 (4 worldwide citation)

A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor ...


10
Renee T Mo, Huiming Bu, Michael P Chudzik, William K Henson, Mukesh V Khare, Vijay Narayanan: High-K metal gate CMOS. International Business Machines Corporation, Scully Scott Murphy & Presser P C, H Daniel Schnurmann, May 17, 2011: US07943460 (3 worldwide citation)

A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric ...



Click the thumbnails below to visualize the patent trend.