1
Hugh M Wilkinson III, George Varghese, Nigel T Poole: Compressed prefix matching database searching. Digital Equipment Corporation, Fish & Richardson P C, July 14, 1998: US05781772 (148 worldwide citation)

Aspects of the invention include a method of conducting a reduced length search along a search path. A node which would otherwise occur between a previous and a following node in the search path is eliminated, and information is stored as to whether, had said eliminated node been present, the search ...


2
Hugh M Wilkinson III, George Varghese, Nigel T Poole: Compressed prefix matching database searching. Cabletron Systems, Wolf Greenfield & Sacks P C, January 11, 2000: US06014659 (54 worldwide citation)

Aspects of the invention include a method of conducting a reduced length search along a search path. A node which would otherwise occur between a previous and a following node in the search path is eliminated, and information is stored as to whether, had said eliminated node been present, the search ...


3
Hugh M Wilkinson III, Matthew J Adiletta, Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, Myles J Wilde: Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section. Intel Corporation, Fish & Richardson P C, August 23, 2005: US06934951 (35 worldwide citation)

A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engine ...


4
Donald F Hooper, Mark B Rosenbluth, Gilbert Wolrich, Matthew J Adiletta, Hugh M Wilkinson III, Robert J Kushlis: Processing a data packet. Intel Corporation, Fish & Richardson P C, October 28, 2008: US07443836 (21 worldwide citation)

A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the exe ...


5
Hugh M Wilkinson III, Matthew J Adiletta, Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, Myles J Wilde: Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access. Intel Corporation, Fish & Richardson P C, November 27, 2007: US07302549 (9 worldwide citation)

A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes processing a sequence of packets with a sequence of threads, with the sequence of threads spanning ...


6
Hugh M Wilkinson III, Mark B Rosenbluth, Matthew J Adiletta, Debra Bernstein, Gilbert Wolrich: Context pipelines. Intel Corporation, Fish & Richardson P C, February 20, 2007: US07181594 (9 worldwide citation)

A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contex ...


7
Sridhar Lakshmanamurthy, Lawrence B Huston, Yim Pun, Raymond Ng, Hugh M Wilkinson III, Mark B Rosenbluth, David Romano: Method and apparatus to communicate flow control information in a duplex network processor system. Intel Corporation, Grossman Tucker Perreault & Pfleger PLLC, July 31, 2007: US07251219 (4 worldwide citation)

In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a ...


8
Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, Matthew J Adiletta, Hugh M Wilkinson III: Registers for data transfers. Intel Corporation, Fish & Richardson P C, October 14, 2008: US07437724 (3 worldwide citation)

A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the regist ...


9
Sridhar Lakshmanamurthy, Lawrence B Huston, Debra Bernstein, Hugh M Wilkinson III, Mark B Rosenbluth: Method and apparatus to process switch traffic. Intel Corporation, Grossman Tucker Perreault & Pfleger PLLC, January 29, 2008: US07324520 (2 worldwide citation)

A system and method for reassembling c-frames into coherent packets are disclosed. C-frames contain segments of a data set. A micro-engine operating multiple threads copies the data set segments into assigned queues, following a thread hierarchy to keep the segments in order. The queues are stored i ...


10
Gilbert Wolrich, Mark B Rosenbluth, Debra Bernstein, Matthew Adiletta, Hugh M Wilkinson III: Registers for data transfers. Intel Corporation, Fish & Richardson PC, May 7, 2009: US20090119671-A1

A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the regist ...