1
Claude L Bertin, Paul A Farrar Sr, Howard L Kalter, Gordon A Kelley Jr, Willem B van der Hoeven, Francis R White: Three dimensional multichip package methods of fabrication. International Business Machines Corporation, Heslin & Rothenberg, December 14, 1993: US05270261 (184 worldwide citation)

A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip having hig ...


2
Claude L Bertin, Wayne J Howell, Erik L Hedberg, Howard L Kalter, Gordon A Kelley Jr: Integrated memory cube structure. International Business Machines Corporation, Heslin & Rothenberg P C, October 1, 1996: US05561622 (158 worldwide citation)

An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is fo ...


3
Claude L Bertin, Paul A Farrar Sr, Howard L Kalter, Gordon A Kelley Jr, Willem B van der Hoeven, Francis R White: Three-dimensional multichip packages and methods of fabrication. International Business Machines Corporation, Heslin & Rothenberg, April 13, 1993: US05202754 (139 worldwide citation)

A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip having hig ...


4
Claude L Bertin, Wayne J Howell, Erik L Hedberg, Howard L Kalter, Gordon A Kelley Jr: Integrated memory cube, structure and fabrication. International Business Machines Corporation, Heslin & Rothenberg P C, October 8, 1996: US05563086 (116 worldwide citation)

An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is fo ...


5
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Howard L Kalter, Jack A Mandelman, Paul A Rabidoux, Jeffrey J Welser: Structure for folded architecture pillar memory cell. International Business Machines Corporation, Mark F Chadurjian, Scully Scott Murphy & Presser, August 27, 2002: US06440801 (107 worldwide citation)

A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are ...


6
Claude L Bertin, Wayne J Howell, Howard L Kalter: Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack. International Business Machines Corporation, Heslin & Rothenberg P C, November 5, 1996: US05571754 (101 worldwide citation)

An endcap chip is provided for a multichip stack comprising multiple integrated circuit chips laminated together. The endcap chip has a substrate with an upper surface and a edge surface, which extends in a plane orthogonal to the upper surface. At least one conductive, monolithic L-connect is dispo ...


7
Kenneth E Beilstein Jr, Claude L Bertin, Howard L Kalter, Gordon A Kelley Jr, Christopher P Miller, Dale E Pontius, Willem B van der Hoeven, Steven Platt: Multichip integrated circuit packages and systems. International Business Machines Corporation, Heslin & Rothenberg, June 20, 1995: US05426566 (94 worldwide citation)

Multichip integrated circuit packages and systems of multichip packages having reduced interconnecting lead lengths are disclosed. The multichip package includes a multiplicity of semiconductor chip layers laminated together in a unitized module. A first metallization pattern is connected to the int ...


8
John A Fifield, Howard L Kalter: Crosstalk-shielded-bit-line dram. International Business Machines Corporation, Howard J Walter Jr, April 23, 1991: US05010524 (94 worldwide citation)

This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit or column lines are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines as an AC ground bus. In its simplest ...


9
Albert S Bergendahl, Claude L Bertin, John E Cronin, Howard L Kalter, Donald M Kenney, Chung H Lam, Hsing San Lee: Method of making shadow RAM cell having a shallow trench EEPROM. International Business Machines Corporation, Heslin & Rothenberg, March 21, 1995: US05399516 (93 worldwide citation)

A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the se ...


10
John E Barth Jr, Charles E Drake, John A Fifield, William P Hovis, Howard L Kalter, Scott C Lewis, Daniel J Nickel, Charles H Stapper, James A Yankosky: Dynamic RAM with on-chip ECC and optimized bit and word redundancy. International Business Machines Corporation, Mark F Chadurjian, July 28, 1992: US05134616 (82 worldwide citation)

A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a s ...