1
Howard G Sachs, James Y Cho: Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency. Intergraph Corporation, Townsend and Townsend, February 25, 1992: US05091846 (128 worldwide citation)

A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation ...


2
Howard G Sachs, Siamak Arya: Software scheduled superscalar computer architecture. Intergraph Corporation, Townsend and Townsend and Crew, September 24, 1996: US05560028 (117 worldwide citation)

A computing system is described in which groups of individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. During compilation of the instructions those which can be ex ...


3
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Apparatus for maintaining consistency of a cache memory with a primary memory. Intergraph Corporation, Townsend and Townsend, June 12, 1990: US04933835 (95 worldwide citation)

A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memor ...


4
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Quadword boundary cache system. Intergraph Corporation, Townsend and Townsend, August 22, 1989: US04860192 (82 worldwide citation)

In a cache memory system, multiple-word boundary registers, multiple-word line registers, and a multiple-word boundary detector system provide accelerated access of data contained within the cache memory within the multiple-word boundaries, and provides for effective prefetch of sequentially ascendi ...


5
Howard G Sachs, James Y Cho: Memory address translation system having modifiable and non-modifiable translation mechanisms. Intergraph Corporation, Townsend and Townsend Khourie and Crew, October 19, 1993: US05255384 (75 worldwide citation)

A Cache-Memory Management System provides high speed virtual to real address translation. Address translation logic, comprised of mutually exclusive modifiable and nonmodifiable translation logic, selectively provides real address output responsive to the externally supplied virtual address from the ...


6
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Cache-MMU system. Intergraph Corporation, Townsend and Townsend, February 6, 1990: US04899275 (57 worldwide citation)

A cache and memory management system architecture and associated protocol is disclosed. The cache and memory management system is comprised of a set associative memory cache subsystem, a set associative translation logic memory subsystem, hardwired page translation, selectable access mode logic, and ...


7
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Method and apparatus for addressing a cache memory. Intergraph Corporation, Townsend & Townsend, November 28, 1989: US04884197 (57 worldwide citation)

A microprocessor architecture is disclosed having separate very high speed instruction and data interface circuitry for coupling via respective separate very high speed instruction and data interface buses to respective external instruction cache and data cache circuitry. The microprocessor is compr ...


8
Howard G Sachs, Siamak Arya: VLIW processor and method therefor. Intergraph Corporation, Townsend and Townsend and Crew, May 10, 2005: US06892293 (28 worldwide citation)

A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the ins ...


9
Howard G Sachs: Instruction cache associative crossbar switch system. Intergraph Corporation, Townsend and Townsend and Crew, August 11, 1998: US05794003 (14 worldwide citation)

A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the ins ...


10
Howard G Sachs: Method and apparatus for translating virtual addresses in a data processing system having multiple instruction pipelines and separate TLBs. Intergraph Corporation, Townsend and Townsend and Crew, October 31, 1995: US05463750 (12 worldwide citation)

A computing system has multiple instruction pipelines, wherein one or more pipelines require translating virtual addresses to real addresses. A TLB is provided for each pipeline requiring address translation services, and an adress translator is provided for each such pipeline for translating a virt ...