1
Eb Eshun
Douglas D Coolbaugh, Ebenezer E Eshun, Ephrem G Gebreselasie, Zhong Xiang He, Herbert Lei Ho, Deok kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Robert Mark Rassel, John Matthew Safran, Kenneth Jay Stein, Norman Whitelaw Robson, Ping Chuan Wang, Hongwen Yan: Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Yuanmin Cai, April 17, 2012: US08159040 (7 worldwide citation)

A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in ...


2
Katherina Babich
Katherina E Babich, Scott D Halle, David V Horak, Arpan P Mahorowala, Wesley C Natzle, Dirk Pfeiffer, Hongwen Yan: Etch selectivity enhancement for tunable etch resistant anti-reflective layer. International Business Machines Corporation, Yuanmin Cai Esq, Hoffman Warnick & D Alessandro, July 18, 2006: US07077903 (4 worldwide citation)

Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA laye ...


3
Katherina Babich
Katherina E Babich, Scott D Halle, David V Horak, Arpan P Mahorowala, Wesley C Natzle, Dirk Pfeiffer, Hongwen Yan: Etch selectivity enhancement for tunable etch resistant anti-reflective layer. International Business Machines Corporation, Hoffman Warnick & D Alessandro, May 12, 2005: US20050098091-A1

Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA laye ...


4
Joyce C Liu, Wesley C Natzle, Richard S Wise, Hongwen Yan, Bidan Zhang: Method for reducing line edge roughness of oxide material using chemical oxide removal. International Business Machines Corporation, James J Cioffi, Cantor Colburn, January 4, 2005: US06838347 (12 worldwide citation)

A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as to transfer a photoresist pattern to the oxide hardmask layer, the photoresist pattern having an initia ...


5
Jeffrey Brown, Richard Wise, Hongwen Yan, Qingyun Yang, Chienfan Yu: Method to controllably form notched polysilicon gate structures. International Business Machines Corporation, April 1, 2003: US06541320 (11 worldwide citation)

A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protect ...


6
Michael P Belyansky, Siddarth A Krishnan, Unoh Kwon, Naim Moumen, Ravikumar Ramachandran, James Kenyon Schaeffer, Richard Wise, Keith Kwong Hon Wong, Hongwen Yan: Method of forming gate stack and structure thereof. International Business Machines Corporation, Freescale Semiconductor, Yuanmin Cai, April 6, 2010: US07691701 (9 worldwide citation)

Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and s ...


7
Bruce Bennett Doris, William K Henson, Richard Stephen Wise, Hongwen Yan: CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs. International Business Machines Corporation, Schmeiser Olsen & Watts, Yuanmin Cai, September 13, 2011: US08018005 (8 worldwide citation)

A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor regi ...


8
Paul C Jamison, Tina Wagner, Richard S Wise, Hongwen Yan: Hard mask process to prevent surface roughness for selective dielectric etching. International Business Machines Corporation, Steven Capella Esq, Scully Scott Murphy & Presser, February 12, 2002: US06345399 (7 worldwide citation)

The propagation of microfissures from a photoresist to an underlying material layer during lithography and etching can be substantially prevented by placing a hard mask between the photoresist and the material layer to be etched. Specifically, the microfissure propagation is substantially prevented ...


9
Tze chiang Chen, Bruce B Doris, Rangarajan Jagannathan, Hongwen Yan, Qingyun Yang, Ying Zhang: Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Robert M Trepp Esq, October 14, 2008: US07435652 (6 worldwide citation)

Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the ...


10
Richard S Wise, Bomy A Chen, Mark C Hakey, Hongwen Yan: Wiring structure for integrated circuit with reduced intralevel capacitance. International Business Machines Corporation, Yuanmin Cai, February 12, 2008: US07329602 (6 worldwide citation)

A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. T ...